[PATCH] drm/amdkfd: limit sdma queue reset caps flagging for gfx9

[Zhang, Jesse(Jie)]

[AMD Official Use Only - AMD Internal Distribution Only]

Reviewed-by: Jesse Zhang <jesse.zhang at amd.com>

-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Jonathan Kim
Sent: Thursday, March 27, 2025 11:54 PM
To: amd-gfx at lists.freedesktop.org
Cc: Belanger, David <David.Belanger at amd.com>; Kasiviswanathan, Harish <Harish.Kasiviswanathan at amd.com>; Kim, Jonathan <Jonathan.Kim at amd.com>
Subject: [PATCH] drm/amdkfd: limit sdma queue reset caps flagging for gfx9

ASICs post GFX 9 are being flagged as SDMA per queue reset supported in the KGD but KFD and scheduler FW currently have no support.
Limit SDMA queue reset capabilities to GFX 9.

Signed-off-by: Jonathan Kim <jonathan.kim at amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index e477d7509646..993eef5a4983 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1983,9 +1983,6 @@ static void kfd_topology_set_capabilities(struct kfd_topology_device *dev)
        if (kfd_dbg_has_ttmps_always_setup(dev->gpu))
                dev->node_props.debug_prop |= HSA_DBG_DISPATCH_INFO_ALWAYS_VALID;

-       if (dev->gpu->adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)
-               dev->node_props.capability2 |= HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED;
-
        if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(10, 0, 0)) {
                if (KFD_GC_VERSION(dev->gpu) == IP_VERSION(9, 4, 3) ||
                    KFD_GC_VERSION(dev->gpu) == IP_VERSION(9, 4, 4)) @@ -2002,6 +1999,9 @@ static void kfd_topology_set_capabilities(struct kfd_topology_device *dev)
                                HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED;

                dev->node_props.capability |= HSA_CAP_PER_QUEUE_RESET_SUPPORTED;
+
+               if (dev->gpu->adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)
+                       dev->node_props.capability2 |=
+HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED;
        } else {
                dev->node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 |
                                        HSA_DBG_WATCH_ADDR_MASK_HI_BIT;
--
2.34.1