[PATCH] drm/amdgpu/vcn4.0.5: Fix GFX10_ADDR_CONFIG programming for vcn1.

[Saleemkhan jamadar]

Looks good to me.
Reviewed by : Saleemkhan Jamadar <saleemkhan.jamadar at amd.com>

On 5/1/2025 5:57 AM, Ruijing Dong wrote:
> The UVD_GFX10_ADDR_CONFIG's offset for vcn1 was programmed
> incorrectly, which causes the corrupted output from VCN1.
>
> This fixes the issue, copied from UVD_GFX10_ADDR_CONFIG
> programming from other VCN generations.
>
> Signed-off-by: Ruijing Dong <ruijing.dong at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index a8cfc63713ad..31cb19e144fe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -563,7 +563,7 @@ static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
>   
>   	/* VCN global tiling registers */
>   	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
> -		VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG),
> +		VCN, 0, regUVD_GFX10_ADDR_CONFIG),
>   		adev->gfx.config.gb_addr_config, 0, indirect);
>   }
>