[PATCH 5/6] drm/amd/amdgpu: Avoid re-parser CSB in gfx_v10_0_cp_gfx_start
Rodrigo Siqueira
siqueira at igalia.com
Sun May 4 21:47:38 UTC 2025
Remove the unnecessary parser of the CSB buffer, and directly use the
result from "adev->gfx.rlc.cs_ptr".
Signed-off-by: Rodrigo Siqueira <siqueira at igalia.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 23 +++++------------------
1 file changed, 5 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 75ea071744eb..36ccb50c274b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -6359,10 +6359,8 @@ static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring;
- const struct cs_section_def *sect = NULL;
- const struct cs_extent_def *ext = NULL;
- int r, i;
- int ctx_reg_offset;
+ u32 csb_size;
+ int r, ctx_reg_offset;
/* init the CP */
WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
@@ -6371,8 +6369,9 @@ static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
gfx_v10_0_cp_gfx_enable(adev, true);
+ csb_size = gfx_v10_0_get_csb_size(adev);
ring = &adev->gfx.gfx_ring[0];
- r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
+ r = amdgpu_ring_alloc(ring, csb_size + 4);
if (r) {
DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
return r;
@@ -6385,19 +6384,7 @@ static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
amdgpu_ring_write(ring, 0x80000000);
amdgpu_ring_write(ring, 0x80000000);
- for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
- for (ext = sect->section; ext->extent != NULL; ++ext) {
- if (sect->id == SECT_CONTEXT) {
- amdgpu_ring_write(ring,
- PACKET3(PACKET3_SET_CONTEXT_REG,
- ext->reg_count));
- amdgpu_ring_write(ring, ext->reg_index -
- PACKET3_SET_CONTEXT_REG_START);
- for (i = 0; i < ext->reg_count; i++)
- amdgpu_ring_write(ring, ext->extent[i]);
- }
- }
- }
+ amdgpu_gfx_write_csb_to_ring(ring, adev->gfx.rlc.cs_ptr, csb_size);
ctx_reg_offset =
SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
--
2.47.2
More information about the amd-gfx
mailing list