[PATCH v2 3/3] drm/amd: Add per-ring reset for vcn v5.0.0 use

[Alex Deucher]

On Tue, May 6, 2025 at 4:50 PM Mario Limonciello
<mario.limonciello at amd.com> wrote:
>
> If there is a problem requiring a reset of the VCN engine, it is better to
> reset the VCN engine rather than the entire GPU.
>
> Add a reset callback for the ring which will stop and start VCN if an
> issue happens.
>
> Signed-off-by: Mario Limonciello <mario.limonciello at amd.com>

Looks good to me.  Series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index b90da3d3e140..27dcc6f37a73 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -196,9 +196,9 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
>                         adev->vcn.inst[i].pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode;
>         }
>
> -       /* TODO: Add queue reset mask when FW fully supports it */
>         adev->vcn.supported_reset =
>                 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
> +       adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
>
>         vcn_v5_0_0_alloc_ip_dump(adev);
>
> @@ -1172,6 +1172,20 @@ static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring)
>         }
>  }
>
> +static int vcn_v5_0_0_ring_reset(struct amdgpu_ring *ring, unsigned int vmid)
> +{
> +       struct amdgpu_device *adev = ring->adev;
> +       struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
> +
> +       if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
> +               return -EOPNOTSUPP;
> +
> +       vcn_v5_0_0_stop(vinst);
> +       vcn_v5_0_0_start(vinst);
> +
> +       return amdgpu_ring_test_helper(ring);
> +}
> +
>  static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = {
>         .type = AMDGPU_RING_TYPE_VCN_ENC,
>         .align_mask = 0x3f,
> @@ -1199,6 +1213,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = {
>         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
>         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
>         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
> +       .reset = vcn_v5_0_0_ring_reset,
>  };
>
>  /**
> --
> 2.49.0
>