[PATCH] drm/amdgpu: add vcn v5_0_0 ip headers

[Alex Deucher]

On Thu, May 8, 2025 at 8:42 AM fanhuang <FangSheng.Huang at amd.com> wrote:
>
> Add vcn v5_0_0 register offset and shift masks
> header files
> Only include the registers required for MMSCH
> initialization
>
> Signed-off-by: fanhuang <FangSheng.Huang at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  .../include/asic_reg/vcn/vcn_5_0_0_offset.h   | 16 +++++++++++++
>  .../include/asic_reg/vcn/vcn_5_0_0_sh_mask.h  | 23 +++++++++++++++++++
>  2 files changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
> index 14574112c469..c4aaa86a95e2 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
> @@ -1147,6 +1147,22 @@
>  #define regUVD_DPG_LMA_CTL2_BASE_IDX                                                                    1
>
>
> +// addressBlock: uvd_mmsch_dec
> +// base address: 0x20d2c
> +#define regMMSCH_VF_VMID                                                                                0x054b
> +#define regMMSCH_VF_VMID_BASE_IDX                                                                       1
> +#define regMMSCH_VF_CTX_ADDR_LO                                                                         0x054c
> +#define regMMSCH_VF_CTX_ADDR_LO_BASE_IDX                                                                1
> +#define regMMSCH_VF_CTX_ADDR_HI                                                                         0x054d
> +#define regMMSCH_VF_CTX_ADDR_HI_BASE_IDX                                                                1
> +#define regMMSCH_VF_CTX_SIZE                                                                            0x054e
> +#define regMMSCH_VF_CTX_SIZE_BASE_IDX                                                                   1
> +#define regMMSCH_VF_MAILBOX_HOST                                                                        0x0552
> +#define regMMSCH_VF_MAILBOX_HOST_BASE_IDX                                                               1
> +#define regMMSCH_VF_MAILBOX_RESP                                                                        0x0553
> +#define regMMSCH_VF_MAILBOX_RESP_BASE_IDX                                                               1
> +
> +
>  // addressBlock: uvd_vcn_umsch_dec
>  // base address: 0x21500
>  #define regVCN_UMSCH_MES_CNTL                                                                           0x0740
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
> index 5c119a6b87fb..bd7242e4e9c6 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
> @@ -5929,6 +5929,29 @@
>  #define UVD_DPG_LMA_CTL2__JPEG_WRITE_PTR_MASK                                                                 0x0000FE00L
>
>
> +// addressBlock: uvd_mmsch_dec
> +//MMSCH_VF_VMID
> +#define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT                                                                     0x0
> +#define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT                                                                   0x5
> +#define MMSCH_VF_VMID__VF_CTX_VMID_MASK                                                                       0x0000001FL
> +#define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK                                                                     0x000003E0L
> +//MMSCH_VF_CTX_ADDR_LO
> +#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT                                                           0x6
> +#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK                                                             0xFFFFFFC0L
> +//MMSCH_VF_CTX_ADDR_HI
> +#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT                                                           0x0
> +#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK                                                             0xFFFFFFFFL
> +//MMSCH_VF_CTX_SIZE
> +#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT                                                                 0x0
> +#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK                                                                   0xFFFFFFFFL
> +//MMSCH_VF_MAILBOX_HOST
> +#define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT                                                                    0x0
> +#define MMSCH_VF_MAILBOX_HOST__DATA_MASK                                                                      0xFFFFFFFFL
> +//MMSCH_VF_MAILBOX_RESP
> +#define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT                                                                    0x0
> +#define MMSCH_VF_MAILBOX_RESP__RESP_MASK                                                                      0xFFFFFFFFL
> +
> +
>  // addressBlock: uvd_vcn_umsch_dec
>  //VCN_UMSCH_MES_CNTL
>  #define VCN_UMSCH_MES_CNTL__PIPE_ID__SHIFT                                                                    0x0
> --
> 2.34.1
>