[PATCH 1/2] drm/amdgpu: read back DB_CTRL register after written for VCN v4.0.5

[Mario Limonciello]

On 5/13/2025 11:29 AM, David (Ming Qiang) Wu wrote:
> On VCN v4.0.5 there is a race condition where the WPTR is not
> updated after starting from idle when doorbell is used. The read-back
> of regVCN_RB1_DB_CTRL register after written is to ensure the
> doorbell_index is updated before it can work properly.
> 
> Link: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12528

As this is a proper fix this tag can be:

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12528

> Signed-off-by: David (Ming Qiang) Wu <David.Wu3 at amd.com>

Make sure the commit message has the stable tag not just the patch email.

Cc: stable at vger.kernel.org

Otherwise:

Reviewed-by: Mario Limonciello <mario.limonciello at amd.com>
Tested-by: Mario Limonciello <mario.limonciello at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index ed00d35039c1..d6be8b05d7a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -1033,6 +1033,8 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
>   	WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
>   			ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
>   			VCN_RB1_DB_CTRL__EN_MASK);
> +	/* Read DB_CTRL to flush the write DB_CTRL command. */
> +	RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);
>   
>   	return 0;
>   }
> @@ -1195,6 +1197,8 @@ static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst)
>   	WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
>   		     ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
>   		     VCN_RB1_DB_CTRL__EN_MASK);
> +	/* Read DB_CTRL to flush the write DB_CTRL command. */
> +	RREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL);
>   
>   	WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
>   	WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));