[PATCH 2/2] drm/amdgpu: read back DB_CTRL register for VCN v4.0.0 and v5.0.0

[Mario Limonciello]

On 5/13/2025 11:29 AM, David (Ming Qiang) Wu wrote:
> Similar to the previous changes made for VCN v4.0.5, the addition of
> register read-back support in VCN v4.0.0 and v5.0.0 is intended to
> prevent potential race conditions, even though such issues have not
> been observed yet. This change ensures consistency across different
> VCN variants and helps avoid similar issues on newer or closely
> related GPUs. The overhead introduced by this read-back is negligible.
> 
> Signed-off-by: David (Ming Qiang) Wu <David.Wu3 at amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c   | 4 ++++
>   drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 ++++
>   2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index 8fff470bce87..24d4077254df 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -1121,6 +1121,8 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
>   	WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
>   			ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
>   			VCN_RB1_DB_CTRL__EN_MASK);
> +	/* Read DB_CTRL to flush the write DB_CTRL command. */
> +	RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);
>   
>   	return 0;
>   }
> @@ -1282,6 +1284,8 @@ static int vcn_v4_0_start(struct amdgpu_vcn_inst *vinst)
>   	WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
>   		     ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
>   		     VCN_RB1_DB_CTRL__EN_MASK);
> +	/* Read DB_CTRL to flush the write DB_CTRL command. */
> +	RREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL);
>   
>   	WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
>   	WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index 27dcc6f37a73..d873128862e4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -793,6 +793,8 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
>   	WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
>   		ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
>   		VCN_RB1_DB_CTRL__EN_MASK);
> +	/* Read DB_CTRL to flush the write DB_CTRL command. */
> +	RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);
>   
>   	return 0;
>   }
> @@ -925,6 +927,8 @@ static int vcn_v5_0_0_start(struct amdgpu_vcn_inst *vinst)
>   	WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
>   		     ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
>   		     VCN_RB1_DB_CTRL__EN_MASK);
> +	/* Read DB_CTRL to flush the write DB_CTRL command. */
> +	RREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL);
>   
>   	WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
>   	WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));