[PATCH v1 2/8] drm/amdgpu: read back register after written

[Dong, Ruijing]

[AMD Official Use Only - AMD Internal Distribution Only]

Only in start() ? what about stop(), pause() and etc?

Thanks,
Ruijing

-----Original Message-----
From: Wu, David <David.Wu3 at amd.com>
Sent: Wednesday, May 14, 2025 1:23 PM
To: amd-gfx at lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher at amd.com>
Cc: Koenig, Christian <Christian.Koenig at amd.com>; Liu, Leo <Leo.Liu at amd.com>; Jiang, Sonny <Sonny.Jiang at amd.com>; Dong, Ruijing <Ruijing.Dong at amd.com>
Subject: [PATCH v1 2/8] drm/amdgpu: read back register after written

The addition of register read-back in VCN v2.0 is intended to prevent potential race conditions.

Signed-off-by: David (Ming Qiang) Wu <David.Wu3 at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index b8d835c9e17e..e6a008d7e67c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -978,6 +978,12 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
        /* Unstall DPG */
        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
                0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
+
+       /* Keeping one read-back to ensure all register writes are done, otherwise
+        * it may introduce race conditions
+        */
+       RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
+
        return 0;
 }

@@ -1152,6 +1158,11 @@ static int vcn_v2_0_start(struct amdgpu_vcn_inst *vinst)
        WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
        fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;

+       /* Keeping one read-back to ensure all register writes are done, otherwise
+        * it may introduce race conditions
+        */
+       RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
+
        return 0;
 }

--
2.49.0