[PATCH v3 9/9] drm/amdgpu: read back register after written

[Dong, Ruijing]

[AMD Official Use Only - AMD Internal Distribution Only]

The series is

`Reviewed-by: Ruijing Dong <ruijing.dong at amd.com>`


-----Original Message-----
From: Wu, David <David.Wu3 at amd.com>
Sent: Wednesday, May 21, 2025 4:24 PM
To: amd-gfx at lists.freedesktop.org; Koenig, Christian <Christian.Koenig at amd.com>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Liu, Leo <Leo.Liu at amd.com>; Jiang, Sonny <Sonny.Jiang at amd.com>; Dong, Ruijing <Ruijing.Dong at amd.com>
Subject: [PATCH v3 9/9] drm/amdgpu: read back register after written

The addition of register read-back in VCN v5.0.1 is intended to prevent potential race conditions.

Signed-off-by: David (Ming Qiang) Wu <David.Wu3 at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
index 1e9d2aedf2799..338cf43c45fe7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
@@ -1038,6 +1038,11 @@ static int vcn_v5_0_1_start(struct amdgpu_vcn_inst *vinst)
        WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
        fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);

+       /* Keeping one read-back to ensure all register writes are done,
+        * otherwise it may introduce race conditions.
+        */
+       RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);
+
        return 0;
 }

@@ -1072,6 +1077,11 @@ static void vcn_v5_0_1_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
        /* disable dynamic power gating mode */
        WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,
                ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
+
+       /* Keeping one read-back to ensure all register writes are done,
+        * otherwise it may introduce race conditions.
+        */
+       RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);
 }

 /**
@@ -1147,6 +1157,11 @@ static int vcn_v5_0_1_stop(struct amdgpu_vcn_inst *vinst)
        /* clear status */
        WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);

+       /* Keeping one read-back to ensure all register writes are done,
+        * otherwise it may introduce race conditions.
+        */
+       RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);
+
        return 0;
 }

--
2.34.1