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+Rex,<br>
<br>
Hi Rex,<br>
do you know if we need to double the CP table size when enabling PG?<br>
<br>
Regards,<br>
David Zhou<br>
<br>
<div class="moz-cite-prefix">On 2016年07月12日 10:15, Tom St Denis
wrote:<br>
</div>
<blockquote
cite="mid:CAAzXoR+ej_+io6mMKsp9iM-qcPc1hXU_SMOJntb8_1EEXHFQhQ@mail.gmail.com"
type="cite">
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<div dir="ltr">Honestly, we don't have documentation handy for the
exact size required when enabling PG (Alex and I) are trying to
sort it out.
<div><br>
</div>
<div>Without the patch both ST and CZ are unstable with PG
enabled. With it so far they both seem to be running fine (I
have a glmark2 + various things) running.</div>
<div><br>
</div>
<div>The final version will be probably somewhere between the
two revisions but for now the old revision isn't stable.</div>
<div><br>
</div>
<div>Tom</div>
<div><br>
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<br>
<div class="gmail_quote">
<div dir="ltr">On Mon, Jul 11, 2016 at 9:57 PM zhoucm1 <<a
moz-do-not-send="true" href="mailto:david1.zhou@amd.com">david1.zhou@amd.com</a>>
wrote:<br>
</div>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
<br>
On 2016年07月12日 05:22, Tom St Denis wrote:<br>
> Was seeing GPU/CPU hangs with previous CP table size.<br>
> With it doubled I've had a full day of uptime while<br>
> running a variety of activities with PG/CG enabled.<br>
What is the root cause? Does the CP table size need 4K
alignment?<br>
We need to identify it before pushing.<br>
<br>
Regards,<br>
David Zhou<br>
><br>
> Signed-off-by: Tom St Denis <<a moz-do-not-send="true"
href="mailto:tom.stdenis@amd.com" target="_blank">tom.stdenis@amd.com</a>><br>
> ---<br>
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-<br>
> 1 file changed, 1 insertion(+), 1 deletion(-)<br>
><br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
> index 24faddbd9a5d..cbbbd5f1da0f 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
> @@ -1293,7 +1293,7 @@ static int gfx_v8_0_rlc_init(struct
amdgpu_device *adev)<br>
><br>
> if ((adev->asic_type == CHIP_CARRIZO) ||<br>
> (adev->asic_type == CHIP_STONEY)) {<br>
> - adev->gfx.rlc.cp_table_size = ALIGN(96 *
5 * 4, 2048) + (64 * 1024); /* JT + GDS */<br>
> + adev->gfx.rlc.cp_table_size = (ALIGN(96
* 5 * 4, 2048) + (64 * 1024)) * 2; /* JT + GDS */<br>
> if (adev->gfx.rlc.cp_table_obj == NULL)
{<br>
> r = amdgpu_bo_create(adev,
adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,<br>
>
AMDGPU_GEM_DOMAIN_VRAM,<br>
<br>
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