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<p>Probably could but I felt that implementation was cleaner.</p>
<p><br>
</p>
<p>Tom</p>
<br>
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<div id="x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> Christian König <deathsimple@vodafone.de><br>
<b>Sent:</b> Tuesday, August 9, 2016 10:56<br>
<b>To:</b> Tom St Denis; amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> StDenis, Tom<br>
<b>Subject:</b> Re: [PATCH 3/3] drm/amd/amdgpu: Simplify bitfield operations in gfx v8</font>
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<div class="PlainText">Am 09.08.2016 um 16:27 schrieb Tom St Denis:<br>
> This patch introduces a new macro WREG32_FIELD which is used<br>
> to write to a register with a new value in a field.  It's designed<br>
> to replace the pattern:<br>
><br>
> tmp = RREG32(mmFoo);<br>
> tmp &= ~REG__FIELD_MASK;<br>
> tmp |= new_value << REG__FIELD__SHIFT;<br>
> WREG32(mmFoo, tmp)<br>
><br>
> with:<br>
><br>
> WREG32_FIELD(Foo, FIELD, new_value);<br>
><br>
> Unlike WREG32_P() it understands offsets/masks and doesn't<br>
> require the caller to shift the value (or mask properly).<br>
><br>
> It's applied where suitable in the gfx_v8_0.c driver to start<br>
> with.<br>
><br>
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com><br>
> ---<br>
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   3 +<br>
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 275 ++++++----------------------------<br>
>   2 files changed, 48 insertions(+), 230 deletions(-)<br>
><br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
> index c309eaf468e9..f23eb38eb3aa 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
> @@ -2218,6 +2218,9 @@ bool amdgpu_device_has_dal_support(struct amdgpu_device *adev);<br>
>   #define REG_GET_FIELD(value, reg, field)                            \<br>
>        (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))<br>
>   <br>
> +#define WREG32_FIELD(reg, field, val)        \<br>
> +     WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))<br>
<br>
Couldn't you use WREG32_P here to implement the new macro?<br>
<br>
Christian.<br>
<br>
> +<br>
>   /*<br>
>    * BIOS helpers.<br>
>    */<br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
> index 5f91a834aed2..6e01392facef 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
> @@ -3566,10 +3566,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)<br>
>        u32 tmp;<br>
>        int i;<br>
>   <br>
> -     tmp = RREG32(mmGRBM_CNTL);<br>
> -     tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);<br>
> -     WREG32(mmGRBM_CNTL, tmp);<br>
> -<br>
> +     WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);<br>
>        WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);<br>
>        WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);<br>
>        WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);<br>
> @@ -3758,9 +3755,7 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)<br>
>                                sizeof(indirect_start_offsets)/sizeof(int));<br>
>   <br>
>        /* save and restore list */<br>
> -     temp = RREG32(mmRLC_SRM_CNTL);<br>
> -     temp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;<br>
> -     WREG32(mmRLC_SRM_CNTL, temp);<br>
> +     WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);<br>
>   <br>
>        WREG32(mmRLC_SRM_ARAM_ADDR, 0);<br>
>        for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)<br>
> @@ -3797,11 +3792,7 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)<br>
>   <br>
>   static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)<br>
>   {<br>
> -     uint32_t data;<br>
> -<br>
> -     data = RREG32(mmRLC_SRM_CNTL);<br>
> -     data |= RLC_SRM_CNTL__SRM_ENABLE_MASK;<br>
> -     WREG32(mmRLC_SRM_CNTL, data);<br>
> +     WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);<br>
>   }<br>
>   <br>
>   static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)<br>
> @@ -3811,75 +3802,34 @@ static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)<br>
>        if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |<br>
>                              AMD_PG_SUPPORT_GFX_SMG |<br>
>                              AMD_PG_SUPPORT_GFX_DMG)) {<br>
> -             data = RREG32(mmCP_RB_WPTR_POLL_CNTL);<br>
> -             data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;<br>
> -             data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);<br>
> -             WREG32(mmCP_RB_WPTR_POLL_CNTL, data);<br>
> -<br>
> -             data = 0;<br>
> -             data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);<br>
> -             data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);<br>
> -             data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);<br>
> -             data |= (0x10 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);<br>
> -             WREG32(mmRLC_PG_DELAY, data);<br>
> +             WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);<br>
>   <br>
> -             data = RREG32(mmRLC_PG_DELAY_2);<br>
> -             data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;<br>
> -             data |= (0x3 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);<br>
> -             WREG32(mmRLC_PG_DELAY_2, data);<br>
> +             data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);<br>
> +             data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);<br>
> +             data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);<br>
> +             data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);<br>
> +             WREG32(mmRLC_PG_DELAY, data);<br>
>   <br>
> -             data = RREG32(mmRLC_AUTO_PG_CTRL);<br>
> -             data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;<br>
> -             data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);<br>
> -             WREG32(mmRLC_AUTO_PG_CTRL, data);<br>
> +             WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);<br>
> +             WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);<br>
>        }<br>
>   }<br>
>   <br>
>   static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,<br>
>                                                bool enable)<br>
>   {<br>
> -     u32 data, orig;<br>
> -<br>
> -     orig = data = RREG32(mmRLC_PG_CNTL);<br>
> -<br>
> -     if (enable)<br>
> -             data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;<br>
> -     else<br>
> -             data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;<br>
> -<br>
> -     if (orig != data)<br>
> -             WREG32(mmRLC_PG_CNTL, data);<br>
> +     WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);<br>
>   }<br>
>   <br>
>   static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,<br>
>                                                  bool enable)<br>
>   {<br>
> -     u32 data, orig;<br>
> -<br>
> -     orig = data = RREG32(mmRLC_PG_CNTL);<br>
> -<br>
> -     if (enable)<br>
> -             data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;<br>
> -     else<br>
> -             data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;<br>
> -<br>
> -     if (orig != data)<br>
> -             WREG32(mmRLC_PG_CNTL, data);<br>
> +     WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);<br>
>   }<br>
>   <br>
>   static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)<br>
>   {<br>
> -     u32 data, orig;<br>
> -<br>
> -     orig = data = RREG32(mmRLC_PG_CNTL);<br>
> -<br>
> -     if (enable)<br>
> -             data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;<br>
> -     else<br>
> -             data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;<br>
> -<br>
> -     if (orig != data)<br>
> -             WREG32(mmRLC_PG_CNTL, data);<br>
> +     WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 1 : 0);<br>
>   }<br>
>   <br>
>   static void gfx_v8_0_init_pg(struct amdgpu_device *adev)<br>
> @@ -3918,34 +3868,24 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev)<br>
>   <br>
>   void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)<br>
>   {<br>
> -     u32 tmp = RREG32(mmRLC_CNTL);<br>
> -<br>
> -     tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);<br>
> -     WREG32(mmRLC_CNTL, tmp);<br>
> +     WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);<br>
>   <br>
>        gfx_v8_0_enable_gui_idle_interrupt(adev, false);<br>
> -<br>
>        gfx_v8_0_wait_for_rlc_serdes(adev);<br>
>   }<br>
>   <br>
>   static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)<br>
>   {<br>
> -     u32 tmp = RREG32(mmGRBM_SOFT_RESET);<br>
> -<br>
> -     tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);<br>
> -     WREG32(mmGRBM_SOFT_RESET, tmp);<br>
> +     WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);<br>
>        udelay(50);<br>
> -     tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);<br>
> -     WREG32(mmGRBM_SOFT_RESET, tmp);<br>
> +<br>
> +     WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);<br>
>        udelay(50);<br>
>   }<br>
>   <br>
>   static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)<br>
>   {<br>
> -     u32 tmp = RREG32(mmRLC_CNTL);<br>
> -<br>
> -     tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);<br>
> -     WREG32(mmRLC_CNTL, tmp);<br>
> +     WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);<br>
>   <br>
>        /* carrizo do enable cp interrupt after cp inited */<br>
>        if (!(adev->flags & AMD_IS_APU))<br>
> @@ -5371,8 +5311,6 @@ static int gfx_v8_0_late_init(void *handle)<br>
>   static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,<br>
>                                                       bool enable)<br>
>   {<br>
> -     uint32_t data, temp;<br>
> -<br>
>        if (adev->asic_type == CHIP_POLARIS11)<br>
>                /* Send msg to SMU via Powerplay */<br>
>                amdgpu_set_powergating_state(adev,<br>
> @@ -5380,83 +5318,35 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade<br>
>                                             enable ?<br>
>                                             AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);<br>
>   <br>
> -     temp = data = RREG32(mmRLC_PG_CNTL);<br>
> -     /* Enable static MGPG */<br>
> -     if (enable)<br>
> -             data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;<br>
> -     else<br>
> -             data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;<br>
> -<br>
> -     if (temp != data)<br>
> -             WREG32(mmRLC_PG_CNTL, data);<br>
> +     WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);<br>
>   }<br>
>   <br>
>   static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,<br>
>                                                        bool enable)<br>
>   {<br>
> -     uint32_t data, temp;<br>
> -<br>
> -     temp = data = RREG32(mmRLC_PG_CNTL);<br>
> -     /* Enable dynamic MGPG */<br>
> -     if (enable)<br>
> -             data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;<br>
> -     else<br>
> -             data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;<br>
> -<br>
> -     if (temp != data)<br>
> -             WREG32(mmRLC_PG_CNTL, data);<br>
> +     WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);<br>
>   }<br>
>   <br>
>   static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,<br>
>                bool enable)<br>
>   {<br>
> -     uint32_t data, temp;<br>
> -<br>
> -     temp = data = RREG32(mmRLC_PG_CNTL);<br>
> -     /* Enable quick PG */<br>
> -     if (enable)<br>
> -             data |= RLC_PG_CNTL__QUICK_PG_ENABLE_MASK;<br>
> -     else<br>
> -             data &= ~RLC_PG_CNTL__QUICK_PG_ENABLE_MASK;<br>
> -<br>
> -     if (temp != data)<br>
> -             WREG32(mmRLC_PG_CNTL, data);<br>
> +     WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);<br>
>   }<br>
>   <br>
>   static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,<br>
>                                          bool enable)<br>
>   {<br>
> -     u32 data, orig;<br>
> -<br>
> -     orig = data = RREG32(mmRLC_PG_CNTL);<br>
> -<br>
> -     if (enable)<br>
> -             data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;<br>
> -     else<br>
> -             data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;<br>
> -<br>
> -     if (orig != data)<br>
> -             WREG32(mmRLC_PG_CNTL, data);<br>
> +     WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);<br>
>   }<br>
>   <br>
>   static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,<br>
>                                                bool enable)<br>
>   {<br>
> -     u32 data, orig;<br>
> -<br>
> -     orig = data = RREG32(mmRLC_PG_CNTL);<br>
> -<br>
> -     if (enable)<br>
> -             data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;<br>
> -     else<br>
> -             data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;<br>
> -<br>
> -     if (orig != data)<br>
> -             WREG32(mmRLC_PG_CNTL, data);<br>
> +     WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);<br>
>   <br>
>        /* Read any GFX register to wake up GFX. */<br>
>        if (!enable)<br>
> -             data = RREG32(mmDB_RENDER_CONTROL);<br>
> +             RREG32(mmDB_RENDER_CONTROL);<br>
>   }<br>
>   <br>
>   static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,<br>
> @@ -5563,10 +5453,10 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,<br>
>   <br>
>   #define MSG_ENTER_RLC_SAFE_MODE     1<br>
>   #define MSG_EXIT_RLC_SAFE_MODE      0<br>
> -<br>
> -#define RLC_GPR_REG2__REQ_MASK           0x00000001<br>
> -#define RLC_GPR_REG2__MESSAGE__SHIFT     0x00000001<br>
> -#define RLC_GPR_REG2__MESSAGE_MASK       0x0000001e<br>
> +#define RLC_GPR_REG2__REQ_MASK 0x00000001<br>
> +#define RLC_GPR_REG2__REQ__SHIFT 0<br>
> +#define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001<br>
> +#define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e<br>
>   <br>
>   static void cz_enter_rlc_safe_mode(struct amdgpu_device *adev)<br>
>   {<br>
> @@ -5596,7 +5486,7 @@ static void cz_enter_rlc_safe_mode(struct amdgpu_device *adev)<br>
>                }<br>
>   <br>
>                for (i = 0; i < adev->usec_timeout; i++) {<br>
> -                     if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0)<br>
> +                     if (!REG_GET_FIELD(RREG32(mmRLC_GPR_REG2), RLC_GPR_REG2, REQ))<br>
>                                break;<br>
>                        udelay(1);<br>
>                }<br>
> @@ -5624,7 +5514,7 @@ static void cz_exit_rlc_safe_mode(struct amdgpu_device *adev)<br>
>        }<br>
>   <br>
>        for (i = 0; i < adev->usec_timeout; i++) {<br>
> -             if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0)<br>
> +             if (!REG_GET_FIELD(RREG32(mmRLC_GPR_REG2), RLC_GPR_REG2, REQ))<br>
>                        break;<br>
>                udelay(1);<br>
>        }<br>
> @@ -5656,7 +5546,7 @@ static void iceland_enter_rlc_safe_mode(struct amdgpu_device *adev)<br>
>                }<br>
>   <br>
>                for (i = 0; i < adev->usec_timeout; i++) {<br>
> -                     if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0)<br>
> +                     if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))<br>
>                                break;<br>
>                        udelay(1);<br>
>                }<br>
> @@ -5683,7 +5573,7 @@ static void iceland_exit_rlc_safe_mode(struct amdgpu_device *adev)<br>
>        }<br>
>   <br>
>        for (i = 0; i < adev->usec_timeout; i++) {<br>
> -             if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0)<br>
> +             if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))<br>
>                        break;<br>
>                udelay(1);<br>
>        }<br>
> @@ -5724,21 +5614,12 @@ static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev<br>
>        /* It is disabled by HW by default */<br>
>        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {<br>
>                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {<br>
> -                     if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {<br>
> +                     if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS)<br>
>                                /* 1 - RLC memory Light sleep */<br>
> -                             temp = data = RREG32(mmRLC_MEM_SLP_CNTL);<br>
> -                             data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;<br>
> -                             if (temp != data)<br>
> -                                     WREG32(mmRLC_MEM_SLP_CNTL, data);<br>
> -                     }<br>
> +                             WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);<br>
>   <br>
> -                     if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {<br>
> -                             /* 2 - CP memory Light sleep */<br>
> -                             temp = data = RREG32(mmCP_MEM_SLP_CNTL);<br>
> -                             data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;<br>
> -                             if (temp != data)<br>
> -                                     WREG32(mmCP_MEM_SLP_CNTL, data);<br>
> -                     }<br>
> +                     if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS)<br>
> +                             WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);<br>
>                }<br>
>   <br>
>                /* 3 - RLC_CGTT_MGCG_OVERRIDE */<br>
> @@ -6213,33 +6094,14 @@ static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,<br>
>   static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,<br>
>                                                 enum amdgpu_interrupt_state state)<br>
>   {<br>
> -     u32 cp_int_cntl;<br>
> -<br>
> -     switch (state) {<br>
> -     case AMDGPU_IRQ_STATE_DISABLE:<br>
> -             cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);<br>
> -             cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,<br>
> -                                         TIME_STAMP_INT_ENABLE, 0);<br>
> -             WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);<br>
> -             break;<br>
> -     case AMDGPU_IRQ_STATE_ENABLE:<br>
> -             cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);<br>
> -             cp_int_cntl =<br>
> -                     REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,<br>
> -                                   TIME_STAMP_INT_ENABLE, 1);<br>
> -             WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);<br>
> -             break;<br>
> -     default:<br>
> -             break;<br>
> -     }<br>
> +     WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,<br>
> +                  state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);<br>
>   }<br>
>   <br>
>   static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,<br>
>                                                     int me, int pipe,<br>
>                                                     enum amdgpu_interrupt_state state)<br>
>   {<br>
> -     u32 mec_int_cntl, mec_int_cntl_reg;<br>
> -<br>
>        /*<br>
>         * amdgpu controls only pipe 0 of MEC1. That's why this function only<br>
>         * handles the setting of interrupts for this specific pipe. All other<br>
> @@ -6249,7 +6111,6 @@ static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,<br>
>        if (me == 1) {<br>
>                switch (pipe) {<br>
>                case 0:<br>
> -                     mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;<br>
>                        break;<br>
>                default:<br>
>                        DRM_DEBUG("invalid pipe %d\n", pipe);<br>
> @@ -6260,22 +6121,8 @@ static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,<br>
>                return;<br>
>        }<br>
>   <br>
> -     switch (state) {<br>
> -     case AMDGPU_IRQ_STATE_DISABLE:<br>
> -             mec_int_cntl = RREG32(mec_int_cntl_reg);<br>
> -             mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,<br>
> -                                          TIME_STAMP_INT_ENABLE, 0);<br>
> -             WREG32(mec_int_cntl_reg, mec_int_cntl);<br>
> -             break;<br>
> -     case AMDGPU_IRQ_STATE_ENABLE:<br>
> -             mec_int_cntl = RREG32(mec_int_cntl_reg);<br>
> -             mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,<br>
> -                                          TIME_STAMP_INT_ENABLE, 1);<br>
> -             WREG32(mec_int_cntl_reg, mec_int_cntl);<br>
> -             break;<br>
> -     default:<br>
> -             break;<br>
> -     }<br>
> +     WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, TIME_STAMP_INT_ENABLE,<br>
> +                  state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);<br>
>   }<br>
>   <br>
>   static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,<br>
> @@ -6283,24 +6130,8 @@ static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,<br>
>                                             unsigned type,<br>
>                                             enum amdgpu_interrupt_state state)<br>
>   {<br>
> -     u32 cp_int_cntl;<br>
> -<br>
> -     switch (state) {<br>
> -     case AMDGPU_IRQ_STATE_DISABLE:<br>
> -             cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);<br>
> -             cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,<br>
> -                                         PRIV_REG_INT_ENABLE, 0);<br>
> -             WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);<br>
> -             break;<br>
> -     case AMDGPU_IRQ_STATE_ENABLE:<br>
> -             cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);<br>
> -             cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,<br>
> -                                         PRIV_REG_INT_ENABLE, 1);<br>
> -             WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);<br>
> -             break;<br>
> -     default:<br>
> -             break;<br>
> -     }<br>
> +     WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,<br>
> +                  state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);<br>
>   <br>
>        return 0;<br>
>   }<br>
> @@ -6310,24 +6141,8 @@ static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,<br>
>                                              unsigned type,<br>
>                                              enum amdgpu_interrupt_state state)<br>
>   {<br>
> -     u32 cp_int_cntl;<br>
> -<br>
> -     switch (state) {<br>
> -     case AMDGPU_IRQ_STATE_DISABLE:<br>
> -             cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);<br>
> -             cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,<br>
> -                                         PRIV_INSTR_INT_ENABLE, 0);<br>
> -             WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);<br>
> -             break;<br>
> -     case AMDGPU_IRQ_STATE_ENABLE:<br>
> -             cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);<br>
> -             cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,<br>
> -                                         PRIV_INSTR_INT_ENABLE, 1);<br>
> -             WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);<br>
> -             break;<br>
> -     default:<br>
> -             break;<br>
> -     }<br>
> +     WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,<br>
> +                  state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);<br>
>   <br>
>        return 0;<br>
>   }<br>
<br>
<br>
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