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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Worth a shot, but I doubt it.  Wptr polling is only enabled if explicitly requested.  I'm not sure if CP PG will work without doorbells since the doorbells
 are handled by the BIF and forwarded to the CP which should wake it if it's gated.  Wptr polling may require CP PG be disabled or prevent it from kicking in.  Probably want to ask the CP team.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Alex<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org]
<b>On Behalf Of </b>StDenis, Tom<br>
<b>Sent:</b> Wednesday, September 28, 2016 9:41 AM<br>
<b>To:</b> Liu, Monk; amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Min, Frank<br>
<b>Subject:</b> Re: [PATCH 8/9] drm/amdgpu:wptr poll address of gfx8 is needed<o:p></o:p></span></p>
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<p><span style="font-family:"Calibri","sans-serif";color:black">Hmm, I wonder if this fix CP power gating issues ... on Carrizo/Stoney...<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black"> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>>
 on behalf of Monk Liu <<a href="mailto:Monk.Liu@amd.com">Monk.Liu@amd.com</a>><br>
<b>Sent:</b> Wednesday, September 28, 2016 04:36<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
<b>Cc:</b> Min, Frank<br>
<b>Subject:</b> [PATCH 8/9] drm/amdgpu:wptr poll address of gfx8 is needed</span><span style="font-family:"Calibri","sans-serif";color:black">
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Calibri","sans-serif";color:black">From: Frank Min <<a href="mailto:Frank.Min@amd.com">Frank.Min@amd.com</a>><br>
<br>
for GFX8, gfx ring's wptr_addr is needed by SRIOV & CP for polling.<br>
<br>
Change-Id: I14477577ef50d1ac90ccc32d41819276811732b7<br>
Signed-off-by: Frank Min <<a href="mailto:Frank.Min@amd.com">Frank.Min@amd.com</a>><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 ++++-<br>
 1 file changed, 4 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
index 097108a..98ef1fe 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
@@ -4338,7 +4338,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)<br>
         struct amdgpu_ring *ring;<br>
         u32 tmp;<br>
         u32 rb_bufsz;<br>
-       u64 rb_addr, rptr_addr;<br>
+       u64 rb_addr, rptr_addr, wptr_gpu_addr;<br>
         int r;<br>
 <br>
         /* Set the write pointer delay */<br>
@@ -4369,6 +4369,9 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)<br>
         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));<br>
         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);<br>
 <br>
+       wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);<br>
+       WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));<br>
+       WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));<br>
         mdelay(1);<br>
         WREG32(mmCP_RB0_CNTL, tmp);<br>
 <br>
-- <br>
1.9.1<br>
<br>
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<p class="MsoNormal" style="margin-top:15.0pt;line-height:15.0pt"><span style="font-size:10.5pt;font-family:"Segoe UI","sans-serif";color:#666666">To see the collection of prior postings to the list, visit the amd-gfx Archives. Using amd-gfx: To post a message
 to all the list members, send email ...<o:p></o:p></span></p>
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