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<p>Hmm, I wonder if this fix CP power gating issues ... on Carrizo/Stoney...</p>
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<div id="x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Monk Liu <Monk.Liu@amd.com><br>
<b>Sent:</b> Wednesday, September 28, 2016 04:36<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Min, Frank<br>
<b>Subject:</b> [PATCH 8/9] drm/amdgpu:wptr poll address of gfx8 is needed</font>
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<div class="PlainText">From: Frank Min <Frank.Min@amd.com><br>
<br>
for GFX8, gfx ring's wptr_addr is needed by SRIOV & CP for polling.<br>
<br>
Change-Id: I14477577ef50d1ac90ccc32d41819276811732b7<br>
Signed-off-by: Frank Min <Frank.Min@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 ++++-<br>
1 file changed, 4 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
index 097108a..98ef1fe 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
@@ -4338,7 +4338,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)<br>
struct amdgpu_ring *ring;<br>
u32 tmp;<br>
u32 rb_bufsz;<br>
- u64 rb_addr, rptr_addr;<br>
+ u64 rb_addr, rptr_addr, wptr_gpu_addr;<br>
int r;<br>
<br>
/* Set the write pointer delay */<br>
@@ -4369,6 +4369,9 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)<br>
WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));<br>
WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);<br>
<br>
+ wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);<br>
+ WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));<br>
+ WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));<br>
mdelay(1);<br>
WREG32(mmCP_RB0_CNTL, tmp);<br>
<br>
-- <br>
1.9.1<br>
<br>
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