<div dir="ltr"><div>No, you can just check if it fails or not (i.e., the ioctl will return -EINVAL if the query is not supported).<br><br></div>Alex<br><div><div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Oct 7, 2016 at 2:33 PM, StDenis, Tom <span dir="ltr"><<a href="mailto:Tom.StDenis@amd.com" target="_blank">Tom.StDenis@amd.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<p>Shouldn't there be a version bump if you're adding a new command to the ioctl?</p>
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<p>Tom</p>
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<div id="m_8418366582461279974x_divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" color="#000000" face="Calibri, sans-serif"><b>From:</b> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org" target="_blank">amd-gfx-bounces@lists.<wbr>freedesktop.org</a>> on behalf of Alex Deucher <<a href="mailto:alexdeucher@gmail.com" target="_blank">alexdeucher@gmail.com</a>><br>
<b>Sent:</b> Friday, October 7, 2016 14:28<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org" target="_blank">amd-gfx@lists.freedesktop.org</a>; Fang, Peter; Zhang, Boyuan<br>
<b>Cc:</b> Deucher, Alexander<br>
<b>Subject:</b> [PATCH 2/6] drm/amdgpu: add info ioctl query for vce clock info</font>
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<div class="m_8418366582461279974PlainText"><div><div class="h5">This is needed to set up the vce clock table in userspace<br>
for proper VCE DPM.<br>
<br>
Signed-off-by: Alex Deucher <<a href="mailto:alexander.deucher@amd.com" target="_blank">alexander.deucher@amd.com</a>><br>
---<br>
include/uapi/drm/amdgpu_drm.h | 18 ++++++++++++++++++<br>
1 file changed, 18 insertions(+)<br>
<br>
diff --git a/include/uapi/drm/amdgpu_drm.<wbr>h b/include/uapi/drm/amdgpu_drm.<wbr>h<br>
index b6a04d4..7cb71f8 100644<br>
--- a/include/uapi/drm/amdgpu_drm.<wbr>h<br>
+++ b/include/uapi/drm/amdgpu_drm.<wbr>h<br>
@@ -491,6 +491,8 @@ struct drm_amdgpu_cs_chunk_data {<br>
#define AMDGPU_INFO_NUM_EVICTIONS <wbr> 0x18<br>
/* Query memory about VRAM and GTT domains */<br>
#define AMDGPU_INFO_MEMORY <wbr> 0x19<br>
+/* Query memory about VRAM and GTT domains */<br>
+#define AMDGPU_INFO_VCE_CLOCK_TABLE <wbr> 0x1A<br>
<br>
#define AMDGPU_INFO_MMR_SE_INDEX_<wbr>SHIFT 0<br>
#define AMDGPU_INFO_MMR_SE_INDEX_MASK <wbr> 0xff<br>
@@ -677,6 +679,22 @@ struct drm_amdgpu_info_hw_ip {<br>
__u32 _pad;<br>
};<br>
<br>
+#define AMDGPU_VCE_CLOCK_TABLE_<wbr>ENTRIES 6<br>
+<br>
+struct drm_amdgpu_info_vce_clock_<wbr>table_entry {<br>
+ /** System clock */<br>
+ __u32 sclk;<br>
+ /** Memory clock */<br>
+ __u32 mclk;<br>
+ /** VCE clock */<br>
+ __u32 eclk;<br>
+ __u32 pad;<br>
+};<br>
+<br>
+struct drm_amdgpu_info_vce_clock_<wbr>table {<br>
+ struct drm_amdgpu_info_vce_clock_<wbr>table_entry entries[AMDGPU_VCE_CLOCK_<wbr>TABLE_ENTRIES];<br>
+};<br>
+<br>
/*<br>
* Supported GPU families<br>
*/<br>
-- <br>
2.5.5<br>
<br></div></div>
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