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<p>I just tried it on my Carrizo this morning (after sending out the dce6 patch) and everything seems peachy.</p>
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<p>Tom</p>
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<div id="x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Deucher, Alexander <Alexander.Deucher@amd.com><br>
<b>Sent:</b> Monday, November 14, 2016 11:56<br>
<b>To:</b> Zhu, Rex; amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Zhu, Rex<br>
<b>Subject:</b> RE: [PATCH] drm/amdgpu: refine cz uvd clock gate logic.</font>
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<div class="PlainText">> -----Original Message-----<br>
> From: amd-gfx [<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">mailto:amd-gfx-bounces@lists.freedesktop.org</a>] On Behalf<br>
> Of Rex Zhu<br>
> Sent: Friday, November 11, 2016 12:25 AM<br>
> To: amd-gfx@lists.freedesktop.org<br>
> Cc: Zhu, Rex<br>
> Subject: [PATCH] drm/amdgpu: refine cz uvd clock gate logic.<br>
> <br>
> sw clockgate was used on uvd6.0.<br>
> when uvd is idle, we gate the uvd clock.<br>
> when decode, we ungate the uvd clock.<br>
> <br>
> Change-Id: I79ecdc5d0f48e97919386a08acca994f1fa05484<br>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com><br>
<br>
Assuming clockgating still works properly:<br>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
<br>
> ---<br>
>  drivers/gpu/drm/amd/amdgpu/cz_dpm.c                       | 6 ++----<br>
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c | 4 ++--<br>
>  2 files changed, 4 insertions(+), 6 deletions(-)<br>
> <br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c<br>
> b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c<br>
> index 41fa351..ba2b66b 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c<br>
> @@ -2111,9 +2111,8 @@ static void cz_dpm_powergate_uvd(struct<br>
> amdgpu_device *adev, bool gate)<br>
> <br>
>        if (gate) {<br>
>                if (pi->caps_uvd_pg) {<br>
> -                     /* disable clockgating so we can properly shut down<br>
> the block */<br>
>                        ret = amdgpu_set_clockgating_state(adev,<br>
> AMD_IP_BLOCK_TYPE_UVD,<br>
> -<br>
> AMD_CG_STATE_UNGATE);<br>
> +<br>
> AMD_CG_STATE_GATE);<br>
>                        if (ret) {<br>
>                                DRM_ERROR("UVD DPM Power Gating failed<br>
> to set clockgating state\n");<br>
>                                return;<br>
> @@ -2159,9 +2158,8 @@ static void cz_dpm_powergate_uvd(struct<br>
> amdgpu_device *adev, bool gate)<br>
>                                return;<br>
>                        }<br>
> <br>
> -                     /* enable clockgating. hw will dynamically<br>
> gate/ungate clocks on the fly */<br>
>                        ret = amdgpu_set_clockgating_state(adev,<br>
> AMD_IP_BLOCK_TYPE_UVD,<br>
> -<br>
> AMD_CG_STATE_GATE);<br>
> +<br>
> AMD_CG_STATE_UNGATE);<br>
>                        if (ret) {<br>
>                                DRM_ERROR("UVD DPM Power Gating Failed<br>
> to set clockgating state\n");<br>
>                                return;<br>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c<br>
> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c<br>
> index 2028980..b0c63c5 100644<br>
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c<br>
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c<br>
> @@ -169,7 +169,7 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr<br>
> *hwmgr, bool bgate)<br>
>        if (bgate) {<br>
>                cgs_set_clockgating_state(hwmgr->device,<br>
>                                                AMD_IP_BLOCK_TYPE_UVD,<br>
> -                                             AMD_CG_STATE_UNGATE);<br>
> +                                             AMD_CG_STATE_GATE);<br>
>                cgs_set_powergating_state(hwmgr->device,<br>
>                                                AMD_IP_BLOCK_TYPE_UVD,<br>
>                                                AMD_PG_STATE_GATE);<br>
> @@ -182,7 +182,7 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr<br>
> *hwmgr, bool bgate)<br>
>                                                AMD_CG_STATE_UNGATE);<br>
>                cgs_set_clockgating_state(hwmgr->device,<br>
>                                                AMD_IP_BLOCK_TYPE_UVD,<br>
> -                                             AMD_PG_STATE_GATE);<br>
> +                                             AMD_PG_STATE_UNGATE);<br>
>                cz_dpm_update_uvd_dpm(hwmgr, false);<br>
>        }<br>
> <br>
> --<br>
> 1.9.1<br>
> <br>
> _______________________________________________<br>
> amd-gfx mailing list<br>
> amd-gfx@lists.freedesktop.org<br>
> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br>
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