<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=gb2312"> <meta name="Generator" content="Microsoft Exchange Server"> <style></style> </head> <body> <meta content="text/html; charset=UTF-8"> <style type="text/css" style="">  </style> <div dir="ltr"> <div id="x_divtagdefaultwrapper" dir="ltr" style="font-size:12pt; color:#000000; font-family:Calibri,Arial,Helvetica,sans-serif"> Hi Alex I agree with you that this patch's GOLDEN setting programming should be put in VI.C, but I found a hardware issue : original linux logic is that we set golden setting registers separately within each IP's hw init routine, but for TONGA VF, it is really strange that we must set all GOLDEN setting value to chip in one shoot (means we use one routine to programing all IP's golden setting to registers), ortherwise we found TONGA vf just failed in RING TEST. and I admit I don't know why (I checked windows CAIL code, it is also set all golden setting registers in one routine) BR Monk </div> <hr tabindex="-1" style="display:inline-block; width:98%"> <div id="x_divRplyFwdMsg" dir="ltr">发件人: Alex Deucher <alexdeucher@gmail.com> 发送时间: 2016年12月20日 7:37:06 收件人: Yu, Xiangliang 抄送: amd-gfx list; dl.SRDC_SW_GPUVirtualization; Min, Frank; Liu, Monk 主题: Re: [PATCH 21/23] drm/amdgpu: change golden register program sequence of virtualization <div> </div> </div> </div> <div class="PlainText">On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu <Xiangliang.Yu@amd.com> wrote: > GPU virtualization has different sequence from normal, change it. > > Signed-off-by: Frank Min <Frank.Min@amd.com> > Signed-off-by: Monk Liu <Monk.Liu@amd.com> > Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 + > drivers/gpu/drm/amd/amdgpu/vi.c | 6 + > drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c | 267 +++++++++++++++++++++++++++++++ > 3 files changed, 275 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h > index eb2905e..e781c9c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h > @@ -84,4 +84,6 @@ int amdgpu_put_gpu(struct amdgpu_device *adev); > /* access vf registers */ > uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); > void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); > + > +void amdgpu_xgpu_init_golden_registers(struct amdgpu_device *adev); > #endif > diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c > index 5229b4a2a..0d5e807 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vi.c > +++ b/drivers/gpu/drm/amd/amdgpu/vi.c > @@ -285,6 +285,12 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) > /* Some of the registers might be dependent on GRBM_GFX_INDEX */ > mutex_lock(&adev->grbm_idx_mutex); > > + if (adev->flags & AMD_IS_VF) { > + amdgpu_xgpu_init_golden_registers(adev); > + mutex_unlock(&adev->grbm_idx_mutex); > + return; > + } > + > switch (adev->asic_type) { > case CHIP_TOPAZ: > amdgpu_program_register_sequence(adev, > diff --git a/drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c > index e5d517f..fa1ee8f 100644 > --- a/drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c > +++ b/drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c > @@ -42,6 +42,273 @@ > #include "dce/dce_10_0_sh_mask.h" > #include "smu/smu_7_1_3_d.h" > > +static const u32 xgpu_fiji_mgcg_cgcg_init[] = { > + mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, > + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, > + mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, > + mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, > + mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, > + mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, > + mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, > + mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, > + mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, > + mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, > + mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, > + mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, > + mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, > + mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, > + mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, > + mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, > + mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, > + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, > + mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, > + mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, > + mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, > + mmPCIE_INDEX, 0xffffffff, 0x0140001c, > + mmPCIE_DATA, 0x000f0000, 0x00000000, > + mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, > + mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, > + mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, > + mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, > + mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, > + mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, > + mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, > + mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, > + mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, > + mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100, > +}; > + > +static const u32 xgpu_golden_settings_fiji_a10[] = { > + mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, > + mmDB_DEBUG2, 0xf00fffff, 0x00000400, > + mmDCI_CLK_CNTL, 0x00000080, 0x00000000, > + mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, > + mmFBC_MISC, 0x1f311fff, 0x12300000, > + mmHDMI_CONTROL, 0x31000111, 0x00000011, > + mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, > + mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, > + mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, > + mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, > + mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, > + mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, > + mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, > + mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, > + mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, > + mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, > + mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, > + mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, > + mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, > + mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff, > + mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, > + mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, > + mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, > + mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, > + mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, > +}; > + > +static const u32 xgpu_fiji_golden_common_all[] = { > + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, > + mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a, > + mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e, > + mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, > + mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, > + mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, > + mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, > + mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, > + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, > + mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009, > +}; > + > +static const u32 xgpu_tonga_mgcg_cgcg_init[] = { > + mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, > + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, > + mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, > + mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, > + mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, > + mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, > + mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, > + mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, > + mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, > + mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, > + mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, > + mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, > + mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, > + mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, > + mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, > + mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, > + mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, > + mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, > + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, > + mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, > + mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, > + mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, > + mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, > + mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, > + mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, > + mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, > + mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, > + mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, > + mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, > + mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, > + mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, > + mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, > + mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, > + mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, > + mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, > + mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, > + mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, > + mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, > + mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, > + mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, > + mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, > + mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, > + mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, > + mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, > + mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, > + mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, > + mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, > + mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, > + mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, > + mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, > + mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, > + mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, > + mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, > + mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, > + mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, > + mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, > + mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, > + mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, > + mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, > + mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, > + mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, > + mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, > + mmPCIE_INDEX, 0xffffffff, 0x0140001c, > + mmPCIE_DATA, 0x000f0000, 0x00000000, > + mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, > + mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, > + mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, > + mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, > + mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, > + mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, > + mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, > + mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, > + mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, > + mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100, > +}; > + > +static const u32 xgpu_golden_settings_tonga_a11[] = { > + mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208, > + mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, > + mmDB_DEBUG2, 0xf00fffff, 0x00000400, > + mmDCI_CLK_CNTL, 0x00000080, 0x00000000, > + mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, > + mmFBC_MISC, 0x1f311fff, 0x12300000, > + mmGB_GPU_ID, 0x0000000f, 0x00000000, > + mmHDMI_CONTROL, 0x31000111, 0x00000011, > + mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, > + mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, > + mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, > + mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, > + mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc, > + mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, > + mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c, > + mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, > + mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, > + mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, > + mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, > + mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, > + mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, > + mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, > + mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, > + mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, > + mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, > + mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, > + mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, > + mmTCC_CTRL, 0x00100000, 0xf31fff7f, > + mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, > + mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb, > + mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, > + mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, > + mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, > + mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, > + mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, > + mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, > + mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, > +}; > + > +static const u32 xgpu_tonga_golden_common_all[] = { > + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, > + mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, > + mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A, > + mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002, > + mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, > + mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, > + mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, > +}; > + > +void amdgpu_xgpu_init_golden_registers(struct amdgpu_device *adev) > +{ > + switch (adev->asic_type) { > + case CHIP_FIJI: > + amdgpu_program_register_sequence(adev, > + xgpu_fiji_mgcg_cgcg_init, > + (const u32)ARRAY_SIZE( > + xgpu_fiji_mgcg_cgcg_init)); > + amdgpu_program_register_sequence(adev, > + xgpu_golden_settings_fiji_a10, > + (const u32)ARRAY_SIZE( > + xgpu_golden_settings_fiji_a10)); > + amdgpu_program_register_sequence(adev, > + xgpu_fiji_golden_common_all, > + (const u32)ARRAY_SIZE( > + xgpu_fiji_golden_common_all)); > + break; > + case CHIP_TONGA: > + amdgpu_program_register_sequence(adev, > + xgpu_tonga_mgcg_cgcg_init, > + (const u32)ARRAY_SIZE( > + xgpu_tonga_mgcg_cgcg_init)); > + amdgpu_program_register_sequence(adev, > + xgpu_golden_settings_tonga_a11, > + (const u32)ARRAY_SIZE( > + xgpu_golden_settings_tonga_a11)); > + amdgpu_program_register_sequence(adev, > + xgpu_tonga_golden_common_all, > + (const u32)ARRAY_SIZE( > + xgpu_tonga_golden_common_all)); > + break; > + default: > + break; > + } > +} Cleaner to just put this in vi.c. Alex > + > static int xgpu_vi_early_init(void *handle) > { > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a> </div> </body> </html>