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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Thank monk’s comments.<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Liu, Monk
<br>
<b>Sent:</b> Tuesday, December 20, 2016 12:09 PM<br>
<b>To:</b> Alex Deucher <alexdeucher@gmail.com>; Yu, Xiangliang <Xiangliang.Yu@amd.com><br>
<b>Cc:</b> amd-gfx list <amd-gfx@lists.freedesktop.org>; dl.SRDC_SW_GPUVirtualization <dl.SRDC_SW_GPUVirtualization@amd.com>; Min, Frank <Frank.Min@amd.com><br>
<b>Subject:</b> </span><span lang="ZH-CN" style="font-size:11.0pt">答复</span><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">: [PATCH 21/23] drm/amdgpu: change golden register program sequence of virtualization<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p><span style="font-family:"Calibri",sans-serif;color:black">Hi Alex<o:p></o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif;color:black"><o:p> </o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif;color:black">I agree with you that this patch's GOLDEN setting programming should be put in VI.C, but I found a hardware issue :<o:p></o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif;color:black"><o:p> </o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif;color:black">original linux logic is that we set golden setting registers separately within each IP's hw init routine, but for TONGA VF, it is really strange that we must set all GOLDEN setting value to chip
 in one shoot (means we use one routine to programing all IP's golden setting to registers), ortherwise we found TONGA vf  just failed in RING TEST.<o:p></o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif;color:black"><o:p> </o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif;color:black">and I admit I don't know why (I checked windows CAIL code, it is also set all golden setting registers in one routine)<o:p></o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif;color:black"><o:p> </o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif;color:black">BR Monk<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span lang="ZH-CN" style="font-size:11.0pt;color:black">发件人</span></b><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">
 Alex Deucher <<a href="mailto:alexdeucher@gmail.com">alexdeucher@gmail.com</a>><br>
</span><b><span lang="ZH-CN" style="font-size:11.0pt;color:black">发送时间</span></b><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black"> 2016</span><span lang="ZH-CN" style="font-size:11.0pt;color:black">年</span><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">12</span><span lang="ZH-CN" style="font-size:11.0pt;color:black">月</span><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">20</span><span lang="ZH-CN" style="font-size:11.0pt;color:black">日</span><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">
 7:37:06<br>
</span><b><span lang="ZH-CN" style="font-size:11.0pt;color:black">收件人</span></b><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black"> Yu, Xiangliang<br>
</span><b><span lang="ZH-CN" style="font-size:11.0pt;color:black">抄送</span></b><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black"> amd-gfx list;
 dl.SRDC_SW_GPUVirtualization; Min, Frank; Liu, Monk<br>
</span><b><span lang="ZH-CN" style="font-size:11.0pt;color:black">主题</span></b><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black"> Re: [PATCH
 21/23] drm/amdgpu: change golden register program sequence of virtualization</span>
<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt">On Sat, Dec 17, 2016 at 11:16 AM, Xiangliang Yu <<a href="mailto:Xiangliang.Yu@amd.com">Xiangliang.Yu@amd.com</a>> wrote:<br>
> GPU virtualization has different sequence from normal, change it.<br>
><br>
> Signed-off-by: Frank Min <<a href="mailto:Frank.Min@amd.com">Frank.Min@amd.com</a>><br>
> Signed-off-by: Monk Liu <<a href="mailto:Monk.Liu@amd.com">Monk.Liu@amd.com</a>><br>
> Signed-off-by: Xiangliang Yu <<a href="mailto:Xiangliang.Yu@amd.com">Xiangliang.Yu@amd.com</a>><br>
> ---<br>
>  drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h |   2 +<br>
>  drivers/gpu/drm/amd/amdgpu/vi.c          |   6 +<br>
>  drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c     | 267 +++++++++++++++++++++++++++++++<br>
>  3 files changed, 275 insertions(+)<br>
><br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h<br>
> index eb2905e..e781c9c 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h<br>
> @@ -84,4 +84,6 @@ int amdgpu_put_gpu(struct amdgpu_device *adev);<br>
>  /* access vf registers */<br>
>  uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);<br>
>  void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);<br>
> +<br>
> +void amdgpu_xgpu_init_golden_registers(struct amdgpu_device *adev);<br>
>  #endif<br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c<br>
> index 5229b4a2a..0d5e807 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c<br>
> @@ -285,6 +285,12 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)<br>
>         /* Some of the registers might be dependent on GRBM_GFX_INDEX */<br>
>         mutex_lock(&adev->grbm_idx_mutex);<br>
><br>
> +       if (adev->flags & AMD_IS_VF) {<br>
> +               amdgpu_xgpu_init_golden_registers(adev);<br>
> +               mutex_unlock(&adev->grbm_idx_mutex);<br>
> +               return;<br>
> +       }<br>
> +<br>
>         switch (adev->asic_type) {<br>
>         case CHIP_TOPAZ:<br>
>                 amdgpu_program_register_sequence(adev,<br>
> diff --git a/drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c<br>
> index e5d517f..fa1ee8f 100644<br>
> --- a/drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c<br>
> +++ b/drivers/gpu/drm/amd/mxgpu/mxgpu_vi.c<br>
> @@ -42,6 +42,273 @@<br>
>  #include "dce/dce_10_0_sh_mask.h"<br>
>  #include "smu/smu_7_1_3_d.h"<br>
><br>
> +static const u32 xgpu_fiji_mgcg_cgcg_init[] = {<br>
> +       mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,<br>
> +       mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,<br>
> +       mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,<br>
> +       mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,<br>
> +       mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,<br>
> +       mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,<br>
> +       mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,<br>
> +       mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,<br>
> +       mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,<br>
> +       mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,<br>
> +       mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,<br>
> +       mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,<br>
> +       mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,<br>
> +       mmPCIE_INDEX, 0xffffffff, 0x0140001c,<br>
> +       mmPCIE_DATA, 0x000f0000, 0x00000000,<br>
> +       mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,<br>
> +       mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,<br>
> +       mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,<br>
> +       mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,<br>
> +       mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,<br>
> +       mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,<br>
> +       mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,<br>
> +       mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,<br>
> +       mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,<br>
> +       mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100,<br>
> +};<br>
> +<br>
> +static const u32 xgpu_golden_settings_fiji_a10[] = {<br>
> +       mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,<br>
> +       mmDB_DEBUG2, 0xf00fffff, 0x00000400,<br>
> +       mmDCI_CLK_CNTL, 0x00000080, 0x00000000,<br>
> +       mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,<br>
> +       mmFBC_MISC, 0x1f311fff, 0x12300000,<br>
> +       mmHDMI_CONTROL, 0x31000111, 0x00000011,<br>
> +       mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,<br>
> +       mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,<br>
> +       mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,<br>
> +       mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,<br>
> +       mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,<br>
> +       mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,<br>
> +       mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,<br>
> +       mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,<br>
> +       mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,<br>
> +       mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,<br>
> +       mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,<br>
> +       mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,<br>
> +       mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,<br>
> +       mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,<br>
> +       mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,<br>
> +       mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,<br>
> +       mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,<br>
> +       mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,<br>
> +       mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,<br>
> +};<br>
> +<br>
> +static const u32 xgpu_fiji_golden_common_all[] = {<br>
> +       mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,<br>
> +       mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,<br>
> +       mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,<br>
> +       mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,<br>
> +       mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,<br>
> +       mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,<br>
> +       mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,<br>
> +       mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,<br>
> +       mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,<br>
> +       mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,<br>
> +};<br>
> +<br>
> +static const u32 xgpu_tonga_mgcg_cgcg_init[] = {<br>
> +       mmRLC_CGTT_MGCG_OVERRIDE,   0xffffffff, 0xffffffff,<br>
> +       mmGRBM_GFX_INDEX,           0xffffffff, 0xe0000000,<br>
> +       mmCB_CGTT_SCLK_CTRL,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_BCI_CLK_CTRL,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_CP_CLK_CTRL,         0xffffffff, 0x00000100,<br>
> +       mmCGTT_CPC_CLK_CTRL,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_CPF_CLK_CTRL,        0xffffffff, 0x40000100,<br>
> +       mmCGTT_DRM_CLK_CTRL0,       0xffffffff, 0x00600100,<br>
> +       mmCGTT_GDS_CLK_CTRL,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_IA_CLK_CTRL,         0xffffffff, 0x06000100,<br>
> +       mmCGTT_PA_CLK_CTRL,         0xffffffff, 0x00000100,<br>
> +       mmCGTT_WD_CLK_CTRL,         0xffffffff, 0x06000100,<br>
> +       mmCGTT_PC_CLK_CTRL,         0xffffffff, 0x00000100,<br>
> +       mmCGTT_RLC_CLK_CTRL,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_SC_CLK_CTRL,         0xffffffff, 0x00000100,<br>
> +       mmCGTT_SPI_CLK_CTRL,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_SQ_CLK_CTRL,         0xffffffff, 0x00000100,<br>
> +       mmCGTT_SQG_CLK_CTRL,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_SX_CLK_CTRL0,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_SX_CLK_CTRL1,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_SX_CLK_CTRL2,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_SX_CLK_CTRL3,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_SX_CLK_CTRL4,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_TCI_CLK_CTRL,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_TCP_CLK_CTRL,        0xffffffff, 0x00000100,<br>
> +       mmCGTT_VGT_CLK_CTRL,        0xffffffff, 0x06000100,<br>
> +       mmDB_CGTT_CLK_CTRL_0,       0xffffffff, 0x00000100,<br>
> +       mmTA_CGTT_CTRL,             0xffffffff, 0x00000100,<br>
> +       mmTCA_CGTT_SCLK_CTRL,       0xffffffff, 0x00000100,<br>
> +       mmTCC_CGTT_SCLK_CTRL,       0xffffffff, 0x00000100,<br>
> +       mmTD_CGTT_CTRL,             0xffffffff, 0x00000100,<br>
> +       mmGRBM_GFX_INDEX,           0xffffffff, 0xe0000000,<br>
> +       mmCGTS_CU0_SP0_CTRL_REG,    0xffffffff, 0x00010000,<br>
> +       mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,<br>
> +       mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,<br>
> +       mmCGTS_CU0_SP1_CTRL_REG,    0xffffffff, 0x00060005,<br>
> +       mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,<br>
> +       mmCGTS_CU1_SP0_CTRL_REG,    0xffffffff, 0x00010000,<br>
> +       mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,<br>
> +       mmCGTS_CU1_TA_CTRL_REG,     0xffffffff, 0x00040007,<br>
> +       mmCGTS_CU1_SP1_CTRL_REG,    0xffffffff, 0x00060005,<br>
> +       mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,<br>
> +       mmCGTS_CU2_SP0_CTRL_REG,    0xffffffff, 0x00010000,<br>
> +       mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,<br>
> +       mmCGTS_CU2_TA_CTRL_REG,     0xffffffff, 0x00040007,<br>
> +       mmCGTS_CU2_SP1_CTRL_REG,    0xffffffff, 0x00060005,<br>
> +       mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,<br>
> +       mmCGTS_CU3_SP0_CTRL_REG,    0xffffffff, 0x00010000,<br>
> +       mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,<br>
> +       mmCGTS_CU3_TA_CTRL_REG,     0xffffffff, 0x00040007,<br>
> +       mmCGTS_CU3_SP1_CTRL_REG,    0xffffffff, 0x00060005,<br>
> +       mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,<br>
> +       mmCGTS_CU4_SP0_CTRL_REG,    0xffffffff, 0x00010000,<br>
> +       mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,<br>
> +       mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,<br>
> +       mmCGTS_CU4_SP1_CTRL_REG,    0xffffffff, 0x00060005,<br>
> +       mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,<br>
> +       mmCGTS_CU5_SP0_CTRL_REG,    0xffffffff, 0x00010000,<br>
> +       mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,<br>
> +       mmCGTS_CU5_TA_CTRL_REG,     0xffffffff, 0x00040007,<br>
> +       mmCGTS_CU5_SP1_CTRL_REG,    0xffffffff, 0x00060005,<br>
> +       mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,<br>
> +       mmCGTS_CU6_SP0_CTRL_REG,    0xffffffff, 0x00010000,<br>
> +       mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,<br>
> +       mmCGTS_CU6_TA_CTRL_REG,     0xffffffff, 0x00040007,<br>
> +       mmCGTS_CU6_SP1_CTRL_REG,    0xffffffff, 0x00060005,<br>
> +       mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,<br>
> +       mmCGTS_CU7_SP0_CTRL_REG,    0xffffffff, 0x00010000,<br>
> +       mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,<br>
> +       mmCGTS_CU7_TA_CTRL_REG,     0xffffffff, 0x00040007,<br>
> +       mmCGTS_CU7_SP1_CTRL_REG,    0xffffffff, 0x00060005,<br>
> +       mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,<br>
> +       mmCGTS_SM_CTRL_REG,         0xffffffff, 0x96e00200,<br>
> +       mmCP_RB_WPTR_POLL_CNTL,     0xffffffff, 0x00900100,<br>
> +       mmRLC_CGCG_CGLS_CTRL,       0xffffffff, 0x0020003c,<br>
> +       mmPCIE_INDEX,               0xffffffff, 0x0140001c,<br>
> +       mmPCIE_DATA,                0x000f0000, 0x00000000,<br>
> +       mmSMC_IND_INDEX_4,          0xffffffff, 0xC060000C,<br>
> +       mmSMC_IND_DATA_4,           0xc0000fff, 0x00000100,<br>
> +       mmXDMA_CLOCK_GATING_CNTL,   0xffffffff, 0x00000100,<br>
> +       mmXDMA_MEM_POWER_CNTL,      0x00000101, 0x00000000,<br>
> +       mmMC_MEM_POWER_LS,          0xffffffff, 0x00000104,<br>
> +       mmCGTT_DRM_CLK_CTRL0,       0xff000fff, 0x00000100,<br>
> +       mmHDP_XDP_CGTT_BLK_CTRL,    0xc0000fff, 0x00000104,<br>
> +       mmCP_MEM_SLP_CNTL,          0x00000001, 0x00000001,<br>
> +       mmSDMA0_CLK_CTRL,           0xff000ff0, 0x00000100,<br>
> +       mmSDMA1_CLK_CTRL,           0xff000ff0, 0x00000100,<br>
> +};<br>
> +<br>
> +static const u32 xgpu_golden_settings_tonga_a11[] = {<br>
> +       mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,<br>
> +       mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,<br>
> +       mmDB_DEBUG2, 0xf00fffff, 0x00000400,<br>
> +       mmDCI_CLK_CNTL, 0x00000080, 0x00000000,<br>
> +       mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,<br>
> +       mmFBC_MISC, 0x1f311fff, 0x12300000,<br>
> +       mmGB_GPU_ID, 0x0000000f, 0x00000000,<br>
> +       mmHDMI_CONTROL, 0x31000111, 0x00000011,<br>
> +       mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,<br>
> +       mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,<br>
> +       mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,<br>
> +       mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,<br>
> +       mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,<br>
> +       mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,<br>
> +       mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,<br>
> +       mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,<br>
> +       mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,<br>
> +       mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,<br>
> +       mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,<br>
> +       mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,<br>
> +       mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,<br>
> +       mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,<br>
> +       mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,<br>
> +       mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,<br>
> +       mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,<br>
> +       mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,<br>
> +       mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,<br>
> +       mmTCC_CTRL, 0x00100000, 0xf31fff7f,<br>
> +       mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,<br>
> +       mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,<br>
> +       mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,<br>
> +       mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,<br>
> +       mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,<br>
> +       mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,<br>
> +       mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,<br>
> +       mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,<br>
> +       mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,<br>
> +};<br>
> +<br>
> +static const u32 xgpu_tonga_golden_common_all[] = {<br>
> +       mmGRBM_GFX_INDEX,               0xffffffff, 0xe0000000,<br>
> +       mmPA_SC_RASTER_CONFIG,          0xffffffff, 0x16000012,<br>
> +       mmPA_SC_RASTER_CONFIG_1,        0xffffffff, 0x0000002A,<br>
> +       mmGB_ADDR_CONFIG,               0xffffffff, 0x22011002,<br>
> +       mmSPI_RESOURCE_RESERVE_CU_0,    0xffffffff, 0x00000800,<br>
> +       mmSPI_RESOURCE_RESERVE_CU_1,    0xffffffff, 0x00000800,<br>
> +       mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,<br>
> +};<br>
> +<br>
> +void amdgpu_xgpu_init_golden_registers(struct amdgpu_device *adev)<br>
> +{<br>
> +       switch (adev->asic_type) {<br>
> +       case CHIP_FIJI:<br>
> +               amdgpu_program_register_sequence(adev,<br>
> +                                                xgpu_fiji_mgcg_cgcg_init,<br>
> +                                                (const u32)ARRAY_SIZE(<br>
> +                                                xgpu_fiji_mgcg_cgcg_init));<br>
> +               amdgpu_program_register_sequence(adev,<br>
> +                                                xgpu_golden_settings_fiji_a10,<br>
> +                                                (const u32)ARRAY_SIZE(<br>
> +                                                xgpu_golden_settings_fiji_a10));<br>
> +               amdgpu_program_register_sequence(adev,<br>
> +                                                xgpu_fiji_golden_common_all,<br>
> +                                                (const u32)ARRAY_SIZE(<br>
> +                                                xgpu_fiji_golden_common_all));<br>
> +               break;<br>
> +       case CHIP_TONGA:<br>
> +               amdgpu_program_register_sequence(adev,<br>
> +                                                xgpu_tonga_mgcg_cgcg_init,<br>
> +                                                (const u32)ARRAY_SIZE(<br>
> +                                                xgpu_tonga_mgcg_cgcg_init));<br>
> +               amdgpu_program_register_sequence(adev,<br>
> +                                                xgpu_golden_settings_tonga_a11,<br>
> +                                                (const u32)ARRAY_SIZE(<br>
> +                                                xgpu_golden_settings_tonga_a11));<br>
> +               amdgpu_program_register_sequence(adev,<br>
> +                                                xgpu_tonga_golden_common_all,<br>
> +                                                (const u32)ARRAY_SIZE(<br>
> +                                                xgpu_tonga_golden_common_all));<br>
> +               break;<br>
> +       default:<br>
> +               break;<br>
> +       }<br>
> +}<br>
<br>
Cleaner to just put this in vi.c.<br>
<br>
Alex<br>
<br>
> +<br>
>  static int xgpu_vi_early_init(void *handle)<br>
>  {<br>
>         struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
> --<br>
> 2.7.4<br>
><br>
> _______________________________________________<br>
> amd-gfx mailing list<br>
> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><o:p></o:p></span></p>
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