<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> <style type="text/css" style="display:none;"></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Arial,Helvetica,sans-serif;" dir="ltr"> It was added late last year so that debugfs mmio could read vce/uvd registers without triggering a race condition between transitions. Cheers, Tom <div style="color: rgb(0, 0, 0);"> <hr tabindex="-1" style="display:inline-block; width:98%"> <div id="divRplyFwdMsg" dir="ltr">From: Koenig, Christian Sent: Friday, January 6, 2017 08:45 To: StDenis, Tom; Huang, Ray; Deucher, Alexander; amd-gfx@lists.freedesktop.org Cc: Kuehling, Felix; Zhang, Hawking; Zhu, Rex; Fu, Ping; Mao, David Subject: Re: [PART1 PATCH v3 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6 <div> </div> </div> <div> <div class="moz-cite-prefix">Good point, I wasn't ware that the pm mutex still existed and is taken under all code flows. Christian. Am 06.01.2017 um 14:42 schrieb StDenis, Tom: </div> <blockquote type="cite"> <div id="divtagdefaultwrapper" dir="ltr" style="font-size:12pt; color:#000000; font-family:Calibri,Arial,Helvetica,sans-serif"> There's already the adev->pm.mutex which is held while gating/ungating blocks. There's no need for a second mutex right? Tom <div style="color:rgb(0,0,0)"> <div> <hr tabindex="-1" style="display:inline-block; width:98%"> <div id="x_divRplyFwdMsg" dir="ltr">From: amd-gfx <a class="moz-txt-link-rfc2396E" href="mailto:amd-gfx-bounces@lists.freedesktop.org"> <amd-gfx-bounces@lists.freedesktop.org></a> on behalf of Christian König <a class="moz-txt-link-rfc2396E" href="mailto:christian.koenig@amd.com"> <christian.koenig@amd.com></a> Sent: Friday, January 6, 2017 07:52 To: Huang, Ray; Deucher, Alexander; <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org"> amd-gfx@lists.freedesktop.org</a> Cc: Kuehling, Felix; Zhang, Hawking; Zhu, Rex; Fu, Ping; Mao, David Subject: Re: [PART1 PATCH v3 7/8] drm/amdgpu: add get clockgating_state method for uvd v5&v6 <div> </div> </div> </div> <div class="PlainText">Am 06.01.2017 um 11:51 schrieb Huang Rui: > Signed-off-by: Huang Rui <a class="moz-txt-link-rfc2396E" href="mailto:ray.huang@amd.com"> <ray.huang@amd.com></a> > --- > > Changes from V2 -> V3: > - add mutex to protect the is_powergated flag. > > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ > drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 37 +++++++++++++++++++++++++++++++++-- > drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 37 +++++++++++++++++++++++++++++++++-- > 3 files changed, 72 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 530549b..afb3ded 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -1183,6 +1183,8 @@ struct amdgpu_uvd { > bool use_ctx_buf; > struct amd_sched_entity entity; > uint32_t srbm_soft_reset; > + bool is_powergated; > + struct mutex pg_mutex; You are missing a mutex_init for pg_mutex, probably best to put this into amdgpu_uvd_sw_init(). Apart from that the patch looks good to me now. Regards, Christian. > }; > > /* > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > index 03a35d9..bf797b8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > @@ -781,16 +781,48 @@ static int uvd_v5_0_set_powergating_state(void *handle, > * the smc and the hw blocks > */ > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > + int ret = 0; > > if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) > return 0; > > + mutex_lock(&adev->uvd.pg_mutex); > + > if (state == AMD_PG_STATE_GATE) { > + adev->uvd.is_powergated = true; > uvd_v5_0_stop(adev); > - return 0; > } else { > - return uvd_v5_0_start(adev); > + ret = uvd_v5_0_start(adev); > + if (ret) > + goto out; > + adev->uvd.is_powergated = false; > + } > + > +out: > + mutex_unlock(&adev->uvd.pg_mutex); > + > + return ret; > +} > + > +static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) > +{ > + struct amdgpu_device *adev = (struct amdgpu_device *)handle; > + int data; > + > + mutex_lock(&adev->uvd.pg_mutex); > + > + if (adev->uvd.is_powergated) { > + DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); > + goto out; > } > + > + /* AMD_CG_SUPPORT_UVD_MGCG */ > + data = RREG32(mmUVD_CGC_CTRL); > + if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) > + *flags |= AMD_CG_SUPPORT_UVD_MGCG; > + > +out: > + mutex_unlock(&adev->uvd.pg_mutex); > } > > static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { > @@ -808,6 +840,7 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { > .soft_reset = uvd_v5_0_soft_reset, > .set_clockgating_state = uvd_v5_0_set_clockgating_state, > .set_powergating_state = uvd_v5_0_set_powergating_state, > + .get_clockgating_state = uvd_v5_0_get_clockgating_state, > }; > > static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > index 8779d4b..0ec692d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > @@ -987,18 +987,50 @@ static int uvd_v6_0_set_powergating_state(void *handle, > * the smc and the hw blocks > */ > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > + int ret = 0; > > if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) > return 0; > > WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); > > + mutex_lock(&adev->uvd.pg_mutex); > + > if (state == AMD_PG_STATE_GATE) { > + adev->uvd.is_powergated = true; > uvd_v6_0_stop(adev); > - return 0; > } else { > - return uvd_v6_0_start(adev); > + ret = uvd_v6_0_start(adev); > + if (ret) > + goto out; > + adev->uvd.is_powergated = false; > + } > + > +out: > + mutex_unlock(&adev->uvd.pg_mutex); > + > + return ret; > +} > + > +static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags) > +{ > + struct amdgpu_device *adev = (struct amdgpu_device *)handle; > + int data; > + > + mutex_lock(&adev->uvd.pg_mutex); > + > + if (adev->uvd.is_powergated) { > + DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); > + goto out; > } > + > + /* AMD_CG_SUPPORT_UVD_MGCG */ > + data = RREG32(mmUVD_CGC_CTRL); > + if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) > + *flags |= AMD_CG_SUPPORT_UVD_MGCG; > + > +out: > + mutex_unlock(&adev->uvd.pg_mutex); > } > > static const struct amd_ip_funcs uvd_v6_0_ip_funcs = { > @@ -1019,6 +1051,7 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = { > .post_soft_reset = uvd_v6_0_post_soft_reset, > .set_clockgating_state = uvd_v6_0_set_clockgating_state, > .set_powergating_state = uvd_v6_0_set_powergating_state, > + .get_clockgating_state = uvd_v6_0_get_clockgating_state, > }; > > static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { _______________________________________________ amd-gfx mailing list <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx" id="LPlnk851602" previewremoved="true">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a> <div id="LPBorder_GT_14837099174670.7732004508767665" style="margin-bottom:20px; overflow:auto; width:100%; text-indent:0px" contenteditable="false"> <table id="LPContainer_14837099174620.9257069430170277" cellspacing="0" style="width:90%; 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