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<p>Just a heads up there is a CG/PG regression.  On the tip of 4.7 I can encode with cg/pg disabled but with it enabled it locks up.</p>
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<p>I'll try to bisect.</p>
<p><br>
</p>
<p>Tom</p>
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<div id="x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Deucher, Alexander <Alexander.Deucher@amd.com><br>
<b>Sent:</b> Monday, January 9, 2017 09:34<br>
<b>To:</b> Zhu, Rex; amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Zhu, Rex<br>
<b>Subject:</b> RE: [PATCH] drm/amdgpu: refine vce3.0 initialize.</font>
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<div class="PlainText">> -----Original Message-----<br>
> From: amd-gfx [<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">mailto:amd-gfx-bounces@lists.freedesktop.org</a>] On Behalf<br>
> Of Rex Zhu<br>
> Sent: Monday, January 09, 2017 8:35 AM<br>
> To: amd-gfx@lists.freedesktop.org<br>
> Cc: Zhu, Rex<br>
> Subject: [PATCH] drm/amdgpu: refine vce3.0 initialize.<br>
> <br>
> 1. disable vce cg when vce hw initialize.<br>
> 2. initizlize vce clock to 10KHz.<br>
> 3: no need to set bypass clock to vce.<br>
> <br>
> Change-Id: I18d5c2debc6688be201af8bb85022ac25020bd8f<br>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com><br>
<br>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
<br>
Does this patch fix this bug by any chance?<br>
<br>
<a href="https://bugzilla.kernel.org/show_bug.cgi?id=191281">https://bugzilla.kernel.org/show_bug.cgi?id=191281</a><br>
<br>
Alex<br>
<br>
> ---<br>
>  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 18 +++---------------<br>
>  drivers/gpu/drm/amd/amdgpu/vi.c       | 32<br>
> +++++++++++++++++++++++++++++++-<br>
>  2 files changed, 34 insertions(+), 16 deletions(-)<br>
> <br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c<br>
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c<br>
> index 5fb0b7f..eb99ee6 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c<br>
> @@ -223,6 +223,9 @@ static int vce_v3_0_start(struct amdgpu_device<br>
> *adev)<br>
>        struct amdgpu_ring *ring;<br>
>        int idx, r;<br>
> <br>
> +     vce_v3_0_override_vce_clock_gating(adev, true); /* force all clocks<br>
> on */<br>
> +     amdgpu_asic_set_vce_clocks(adev, 10000, 10000);<br>
> +<br>
>        ring = &adev->vce.ring[0];<br>
>        WREG32(mmVCE_RB_RPTR, ring->wptr);<br>
>        WREG32(mmVCE_RB_WPTR, ring->wptr);<br>
> @@ -701,17 +704,7 @@ static int vce_v3_0_process_interrupt(struct<br>
> amdgpu_device *adev,<br>
>        return 0;<br>
>  }<br>
> <br>
> -static void vce_v3_0_set_bypass_mode(struct amdgpu_device *adev, bool<br>
> enable)<br>
> -{<br>
> -     u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);<br>
> -<br>
> -     if (enable)<br>
> -             tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;<br>
> -     else<br>
> -             tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;<br>
> <br>
> -     WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);<br>
> -}<br>
> <br>
>  static int vce_v3_0_set_clockgating_state(void *handle,<br>
>                                          enum amd_clockgating_state state)<br>
> @@ -720,11 +713,6 @@ static int vce_v3_0_set_clockgating_state(void<br>
> *handle,<br>
>        bool enable = (state == AMD_CG_STATE_GATE) ? true : false;<br>
>        int i;<br>
> <br>
> -     if ((adev->asic_type == CHIP_POLARIS10) ||<br>
> -             (adev->asic_type == CHIP_TONGA) ||<br>
> -             (adev->asic_type == CHIP_FIJI))<br>
> -             vce_v3_0_set_bypass_mode(adev, enable);<br>
> -<br>
>        if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))<br>
>                return 0;<br>
> <br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c<br>
> b/drivers/gpu/drm/amd/amdgpu/vi.c<br>
> index 16ba943..b9924e3 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c<br>
> @@ -789,7 +789,37 @@ static int vi_set_uvd_clocks(struct amdgpu_device<br>
> *adev, u32 vclk, u32 dclk)<br>
> <br>
>  static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32<br>
> ecclk)<br>
>  {<br>
> -     /* todo */<br>
> +     int r, i;<br>
> +     struct atom_clock_dividers dividers;<br>
> +     u32 tmp;<br>
> +<br>
> +     r = amdgpu_atombios_get_clock_dividers(adev,<br>
> +<br>
> COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,<br>
> +                                            ecclk, false, &dividers);<br>
> +     if (r)<br>
> +             return r;<br>
> +<br>
> +     for (i = 0; i < 100; i++) {<br>
> +             if (RREG32_SMC(ixCG_ECLK_STATUS) &<br>
> CG_ECLK_STATUS__ECLK_STATUS_MASK)<br>
> +                     break;<br>
> +             mdelay(10);<br>
> +     }<br>
> +     if (i == 100)<br>
> +             return -ETIMEDOUT;<br>
> +<br>
> +     tmp = RREG32_SMC(ixCG_ECLK_CNTL);<br>
> +     tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |<br>
> +             CG_ECLK_CNTL__ECLK_DIVIDER_MASK);<br>
> +     tmp |= dividers.post_divider;<br>
> +     WREG32_SMC(ixCG_ECLK_CNTL, tmp);<br>
> +<br>
> +     for (i = 0; i < 100; i++) {<br>
> +             if (RREG32_SMC(ixCG_ECLK_STATUS) &<br>
> CG_ECLK_STATUS__ECLK_STATUS_MASK)<br>
> +                     break;<br>
> +             mdelay(10);<br>
> +     }<br>
> +     if (i == 100)<br>
> +             return -ETIMEDOUT;<br>
> <br>
>        return 0;<br>
>  }<br>
> --<br>
> 1.9.1<br>
> <br>
> _______________________________________________<br>
> amd-gfx mailing list<br>
> amd-gfx@lists.freedesktop.org<br>
> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br>
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