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      <blockquote type="cite">The changes to the GFX6/7/8 look
        reasonable though only question is you read from
        <span style="font-family: Calibri, Arial, Helvetica, sans-serif,
          "Apple Color Emoji", "Segoe UI Emoji",
          NotoColorEmoji, "Segoe UI Symbol", "Android
          Emoji", EmojiSymbols; font-size: 13.3333px;">
          mmVM_PRT_CNTL</span> and then write to <span
          style="font-family: Calibri, Arial, Helvetica, sans-serif,
          "Apple Color Emoji", "Segoe UI Emoji",
          NotoColorEmoji, "Segoe UI Symbol", "Android
          Emoji", EmojiSymbols; font-size: 13.3333px;">
          mmVM_CONTEXT1_CNTL</span> .  Is that expected?</blockquote>
      Not at all! Looks like a copy&paste error while modifying the
      original patch. Thanks for catching this.<br>
      <br>
      Also the whole set is so far only compile tested, still need to
      give it a run on all hardware generations anyway.<br>
      <br>
      Christian.<br>
      <br>
      Am 30.01.2017 um 14:59 schrieb StDenis, Tom:<br>
    </div>
    <blockquote
cite="mid:CY4PR12MB1768231152C68AFABF76535AF74B0@CY4PR12MB1768.namprd12.prod.outlook.com"
      type="cite">
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style="font-size:12pt;color:#000000;font-family:Calibri,Arial,Helvetica,sans-serif;"
        dir="ltr">
        <p>Minor nit: the comment says v8 <img class="EmojiInsert"
            id="OWAEmoji249760" alt="😊" style="vertical-align: bottom;"
            src="cid:part1.A7DC9569.EFDA65F4@vodafone.de"></p>
        <p><br>
        </p>
        <p>The changes to the GFX6/7/8 look reasonable though only
          question is you read from
          <span style="font-family: Calibri, Arial, Helvetica,
            sans-serif, "Apple Color Emoji", "Segoe UI
            Emoji", NotoColorEmoji, "Segoe UI Symbol",
            "Android Emoji", EmojiSymbols; font-size:
            13.3333px;">
            mmVM_PRT_CNTL</span> and then write to <span
            style="font-family: Calibri, Arial, Helvetica, sans-serif,
            "Apple Color Emoji", "Segoe UI Emoji",
            NotoColorEmoji, "Segoe UI Symbol", "Android
            Emoji", EmojiSymbols; font-size: 13.3333px;">
            mmVM_CONTEXT1_CNTL</span> .  Is that expected?</p>
        <p><br>
        </p>
        <p>Tom</p>
        <br>
        <br>
        <div style="color: rgb(0, 0, 0);">
          <div>
            <hr tabindex="-1" style="display:inline-block; width:98%">
            <div id="x_divRplyFwdMsg" dir="ltr"><font
                style="font-size:11pt" color="#000000" face="Calibri,
                sans-serif"><b>From:</b> amd-gfx
                <a class="moz-txt-link-rfc2396E" href="mailto:amd-gfx-bounces@lists.freedesktop.org"><amd-gfx-bounces@lists.freedesktop.org></a> on behalf
                of Christian König <a class="moz-txt-link-rfc2396E" href="mailto:deathsimple@vodafone.de"><deathsimple@vodafone.de></a><br>
                <b>Sent:</b> Monday, January 30, 2017 07:57<br>
                <b>To:</b> <a class="moz-txt-link-abbreviated" href="mailto:bas@basnieuwenhuizen.nl">bas@basnieuwenhuizen.nl</a>; <a class="moz-txt-link-abbreviated" href="mailto:airlied@gmail.com">airlied@gmail.com</a><br>
                <b>Cc:</b> <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
                <b>Subject:</b> [PATCH 4/6] drm/amdgpu: implement PRT
                for GFX6</font>
              <div> </div>
            </div>
          </div>
          <font size="2"><span style="font-size:10pt;">
              <div class="PlainText">From: Christian König
                <a class="moz-txt-link-rfc2396E" href="mailto:christian.koenig@amd.com"><christian.koenig@amd.com></a><br>
                <br>
                Enable/disable the handling globally for now and<br>
                print a warning when we enable it for the first time.<br>
                <br>
                Signed-off-by: Christian König
                <a class="moz-txt-link-rfc2396E" href="mailto:christian.koenig@amd.com"><christian.koenig@amd.com></a><br>
                ---<br>
                 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 63
                +++++++++++++++++++++++++++++++++++<br>
                 1 file changed, 63 insertions(+)<br>
                <br>
                diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
                b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c<br>
                index e2b0b16..c23503e 100644<br>
                --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c<br>
                +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c<br>
                @@ -398,6 +398,68 @@ static void
                gmc_v6_0_set_fault_enable_default(struct amdgpu_device
                *adev,<br>
                         WREG32(mmVM_CONTEXT1_CNTL, tmp);<br>
                 }<br>
                 <br>
                + /**<br>
                +   + * gmc_v8_0_set_prt - set PRT VM fault<br>
                +   + *<br>
                +   + * @adev: amdgpu_device pointer<br>
                +   + * @enable: enable/disable VM fault handling for
                PRT<br>
                +   +*/<br>
                +static void gmc_v6_0_set_prt(struct amdgpu_device
                *adev, bool enable)<br>
                +{<br>
                +       u32 tmp;<br>
                +<br>
                +       if (enable && !adev->mc.prt_warning)
                {<br>
                +               dev_warn(adev->dev, "Disabling VM
                faults because of PRT request!\n");<br>
                +               adev->mc.prt_warning = true;<br>
                +       }<br>
                +<br>
                +       tmp = RREG32(mmVM_PRT_CNTL);<br>
                +       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,<br>
                +                          
                CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,<br>
                +                           enable);<br>
                +       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,<br>
                +                          
                CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,<br>
                +                           enable);<br>
                +       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,<br>
                +                          
                TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS,<br>
                +                           enable);<br>
                +       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,<br>
                +                          
                TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS,<br>
                +                           enable);<br>
                +       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,<br>
                +                          
                L2_CACHE_STORE_INVALID_ENTRIES,<br>
                +                           enable);<br>
                +       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,<br>
                +                          
                L1_TLB_STORE_INVALID_ENTRIES,<br>
                +                           enable);<br>
                +       tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,<br>
                +                           MASK_PDE0_FAULT, enable);<br>
                +       WREG32(mmVM_CONTEXT1_CNTL, tmp);<br>
                +<br>
                +       if (enable) {<br>
                +               uint32_t low = AMDGPU_VA_RESERVED_SIZE
                >> AMDGPU_GPU_PAGE_SHIFT;<br>
                +               uint32_t high =
                adev->vm_manager.max_pfn;<br>
                +<br>
                +               WREG32(mmVM_PRT_APERTURE0_LOW_ADDR,
                low);<br>
                +               WREG32(mmVM_PRT_APERTURE1_LOW_ADDR,
                low);<br>
                +               WREG32(mmVM_PRT_APERTURE2_LOW_ADDR,
                low);<br>
                +               WREG32(mmVM_PRT_APERTURE3_LOW_ADDR,
                low);<br>
                +               WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR,
                high);<br>
                +               WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR,
                high);<br>
                +               WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR,
                high);<br>
                +               WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR,
                high);<br>
                +       } else {<br>
                +               WREG32(mmVM_PRT_APERTURE0_LOW_ADDR,
                0xfffffff);<br>
                +               WREG32(mmVM_PRT_APERTURE1_LOW_ADDR,
                0xfffffff);<br>
                +               WREG32(mmVM_PRT_APERTURE2_LOW_ADDR,
                0xfffffff);<br>
                +               WREG32(mmVM_PRT_APERTURE3_LOW_ADDR,
                0xfffffff);<br>
                +               WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR,
                0x0);<br>
                +               WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR,
                0x0);<br>
                +               WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR,
                0x0);<br>
                +               WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR,
                0x0);<br>
                +       }<br>
                +}<br>
                +<br>
                 static int gmc_v6_0_gart_enable(struct amdgpu_device
                *adev)<br>
                 {<br>
                         int r, i;<br>
                @@ -1080,6 +1142,7 @@ static const struct amd_ip_funcs
                gmc_v6_0_ip_funcs = {<br>
                 static const struct amdgpu_gart_funcs
                gmc_v6_0_gart_funcs = {<br>
                         .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,<br>
                         .set_pte_pde = gmc_v6_0_gart_set_pte_pde,<br>
                +       .set_prt = gmc_v6_0_set_prt,<br>
                 };<br>
                 <br>
                 static const struct amdgpu_irq_src_funcs
                gmc_v6_0_irq_funcs = {<br>
                -- <br>
                2.5.0<br>
                <br>
                _______________________________________________<br>
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