<div dir="ltr"><div class="gmail_extra"><br><div class="gmail_quote">On 24 April 2017 at 10:51, Christian König <span dir="ltr"><<a href="mailto:deathsimple@vodafone.de" target="_blank">deathsimple@vodafone.de</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><span class="gmail-">Am 24.04.2017 um 11:42 schrieb Julien Isorce:<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
But re-add the flag is the bo is moved back to vram.<br>
<br>
This fixes "ring 0/3 stalled" issue which happens when the driver<br>
evicts bo from vram to gtt, at least on TAHITI and CAPVERDE.<br>
</blockquote>
<br></span>
Interesting find, but NAK on the approach for fixing it.<br></blockquote><div><br></div><div>Thx for the comments.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<br>
If WC mappings don't work for TAHITI and CAPVERDE we need to figure out why or at least disable them for those hardware generations in general.<br></blockquote><div><br></div><div>Should I extend <a href="https://cgit.freedesktop.org/~agd5f/linux/tree/drivers/gpu/drm/radeon/radeon_object.c?h=amd-staging-4.9#n228">https://cgit.freedesktop.org/~agd5f/linux/tree/drivers/gpu/drm/radeon/radeon_object.c?h=amd-staging-4.9#n228</a> to BONAIRE (which will include VERDE and TAHITI) ? (to match <a href="https://cgit.freedesktop.org/~agd5f/linux/tree/drivers/gpu/drm/radeon/radeon_ib.c?h=amd-staging-4.9#n199">https://cgit.freedesktop.org/~agd5f/linux/tree/drivers/gpu/drm/radeon/radeon_ib.c?h=amd-staging-4.9#n199</a> )<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
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Disabling WC for BOs swapped out from VRAM won't buy us much if the BO was initially created in GTT anyway.</blockquote><div><br></div><div>Initially created in VRAM: <a href="https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/radeon/r600_buffer_common.c#n164">https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/radeon/r600_buffer_common.c#n164</a></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><span class="gmail-HOEnZb"><font color="#888888"><br>
<br>
Christian.</font></span><div class="gmail-HOEnZb"><div class="gmail-h5"><br>
<br>
<blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<br>
I do not know the exact reason among the following:<br>
- si_copy_dma from vram to gtt is slow if WC<br>
(only for the non-visible part ? specific cases ?)<br>
- Allow snooping (SNOOPED flag from radeon_vm_bo_update).<br>
- WC should not be set at all for bo in the GTT<br>
(same reason why WC is only set for vram domain,<br>
see mesa::r600_init_resource_field<wbr>s since mesa commit 5b6a0b7<br>
"gallium/radeon: set GTT WC on tiled textures")<br>
- Bug in WC<br>
- Same reason as why radeon_sa_bo_manager_init is not passing<br>
WC flags if older than CHIP_BONAIRE (see 810b73d1<br>
drm/radeon: Use write-combined CPU mappings of IBs on >= CIK)<br>
- Same as b738ca5d<br>
Revert "drm/radeon: Use write-combined CPU mappings of ring ..."<br>
- Same as 96ea47c0<br>
drm/radeon: Disable uncacheable CPU mappings of GTT with RV6xx<br>
see <a href="https://bugs.freedesktop.org/show_bug.cgi?id=91268#c2" rel="noreferrer" target="_blank">https://bugs.freedesktop.org/s<wbr>how_bug.cgi?id=91268#c2</a><br>
<br>
<a href="https://bugs.freedesktop.org/show_bug.cgi?id=100712" rel="noreferrer" target="_blank">https://bugs.freedesktop.org/s<wbr>how_bug.cgi?id=100712</a><br>
---<br>
drivers/gpu/drm/radeon/radeon.<wbr>h | 1 +<br>
drivers/gpu/drm/radeon/radeon_<wbr>object.c | 1 +<br>
drivers/gpu/drm/radeon/radeon_<wbr>ttm.c | 13 +++++++++++++<br>
3 files changed, 15 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/radeon/radeo<wbr>n.h b/drivers/gpu/drm/radeon/radeo<wbr>n.h<br>
index 7a39a35..9847f4e 100644<br>
--- a/drivers/gpu/drm/radeon/radeo<wbr>n.h<br>
+++ b/drivers/gpu/drm/radeon/radeo<wbr>n.h<br>
@@ -518,6 +518,7 @@ struct radeon_bo {<br>
struct radeon_mn *mn;<br>
struct list_head mn_list;<br>
+ u32 vram_flags;<br>
};<br>
#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)<br>
diff --git a/drivers/gpu/drm/radeon/radeo<wbr>n_object.c b/drivers/gpu/drm/radeon/radeo<wbr>n_object.c<br>
index a557869..870f6b0 100644<br>
--- a/drivers/gpu/drm/radeon/radeo<wbr>n_object.c<br>
+++ b/drivers/gpu/drm/radeon/radeo<wbr>n_object.c<br>
@@ -228,6 +228,7 @@ int radeon_bo_create(struct radeon_device *rdev,<br>
RADEON_GEM_DOMAIN_CPU);<br>
bo->flags = flags;<br>
+ bo->vram_flags = 0;<br>
/* PCI GART is always snooped */<br>
if (!(rdev->flags & RADEON_IS_PCIE))<br>
bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);<br>
diff --git a/drivers/gpu/drm/radeon/radeo<wbr>n_ttm.c b/drivers/gpu/drm/radeon/radeo<wbr>n_ttm.c<br>
index d07ff84..a8743bd 100644<br>
--- a/drivers/gpu/drm/radeon/radeo<wbr>n_ttm.c<br>
+++ b/drivers/gpu/drm/radeon/radeo<wbr>n_ttm.c<br>
@@ -440,6 +440,19 @@ static int radeon_bo_move(struct ttm_buffer_object *bo,<br>
r = radeon_move_ram_vram(bo, evict, interruptible,<br>
no_wait_gpu, new_mem);<br>
} else {<br>
+ /* Clear WC flag when moving bo from vram to gtt. */<br>
+ if (old_mem->mem_type == TTM_PL_VRAM && new_mem->mem_type == TTM_PL_TT) {<br>
+ if (rbo->flags & RADEON_GEM_GTT_WC) {<br>
+ rbo->vram_flags |= RADEON_GEM_GTT_WC;<br>
+ rbo->flags &= ~RADEON_GEM_GTT_WC;<br>
+ }<br>
+ /* Re-add WC flag when moving back from gtt to vram. */<br>
+ } else if (old_mem->mem_type == TTM_PL_TT && new_mem->mem_type == TTM_PL_VRAM) {<br>
+ if (rbo->vram_flags & RADEON_GEM_GTT_WC) {<br>
+ rbo->flags |= RADEON_GEM_GTT_WC;<br>
+ rbo->vram_flags &= ~RADEON_GEM_GTT_WC;<br>
+ }<br>
+ }<br>
r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);<br>
}<br>
<br>
</blockquote>
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