<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> </head> <body text="#000000" bgcolor="#FFFFFF"> Hi Alex, In Catalyst driver source code, Stoney is listed as supported, I don't know how well it is supported though. I think at least people have run some graphic operations. What kind of hangs happens in Stoney? Is it a graphic operation hang? Or OpenCL? Or something else? How easily it is reproduced? Stoney is similar to Carizzo. People has tried computes on Carrizo till Fiji in fglrx. At least, we need to limit this change for Stoney only unless it is reported in other ASICs too. This change can affect compute performance a lot. People are evaluating even the AMDGPU PRO OpenCL on FIJI, as far as I know. Thanks, Alex Bin <div class="moz-cite-prefix">On 2017-06-07 12:32 PM, Deucher, Alexander wrote: </div> <blockquote type="cite" cite="mid:BN6PR12MB1652FFCD2FC9C923271C1475F7C80@BN6PR12MB1652.namprd12.prod.outlook.com"> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> <meta name="Generator" content="Microsoft Exchange Server">  <style></style> <div class="PlainText">> -----Original Message----- > From: Xie, AlexBin > Sent: Wednesday, June 07, 2017 12:31 PM > To: Alex Deucher; <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> > Cc: Deucher, Alexander > Subject: Re: [PATCH 1/3] drm/amdgpu: fix mec queue policy on single MEC > asics > > Hi Alex, > > In closed source driver, we assign compute queues to all 4 pipes always. > There is no hangs. > > May I know which ASIC? It was reported on Stoney. Alex > > Assign all queues in first pipe first mec can slow things down. > > Thanks, > > Alex Bin Xie > > > > On 2017-06-07 11:10 AM, Alex Deucher wrote: > > Fixes hangs on single MEC asics. > > > > Fixes: 2ed286fb434 (drm/amdgpu: new queue policy, take first 2 queues of > each pipe v2) > > Signed-off-by: Alex Deucher <a class="moz-txt-link-rfc2396E" href="mailto:alexander.deucher@amd.com"><alexander.deucher@amd.com></a> > > --- > > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 12 +++++++++--- > > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 +++++++++--- > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++++++++--- > > 3 files changed, 27 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > index 4c04e9d..862bc72 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > @@ -2825,9 +2825,15 @@ static void > gfx_v7_0_compute_queue_acquire(struct amdgpu_device *adev) > > if (mec >= adev->gfx.mec.num_mec) > > break; > > > > - /* policy: amdgpu owns the first two queues of the first MEC > */ > > - if (mec == 0 && queue < 2) > > - set_bit(i, adev->gfx.mec.queue_bitmap); > > + if (adev->gfx.mec.num_mec > 1) { > > + /* policy: amdgpu owns the first two queues of the > first MEC */ > > + if (mec == 0 && queue < 2) > > + set_bit(i, adev->gfx.mec.queue_bitmap); > > + } else { > > + /* policy: amdgpu owns all queues in the first pipe */ > > + if (mec == 0 && pipe == 0) > > + set_bit(i, adev->gfx.mec.queue_bitmap); > > + } > > } > > > > /* update the number of active compute rings */ > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > index ad2e0bb..1370b39 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > @@ -1464,9 +1464,15 @@ static void > gfx_v8_0_compute_queue_acquire(struct amdgpu_device *adev) > > if (mec >= adev->gfx.mec.num_mec) > > break; > > > > - /* policy: amdgpu owns the first two queues of the first MEC > */ > > - if (mec == 0 && queue < 2) > > - set_bit(i, adev->gfx.mec.queue_bitmap); > > + if (adev->gfx.mec.num_mec > 1) { > > + /* policy: amdgpu owns the first two queues of the > first MEC */ > > + if (mec == 0 && queue < 2) > > + set_bit(i, adev->gfx.mec.queue_bitmap); > > + } else { > > + /* policy: amdgpu owns all queues in the first pipe */ > > + if (mec == 0 && pipe == 0) > > + set_bit(i, adev->gfx.mec.queue_bitmap); > > + } > > } > > > > /* update the number of active compute rings */ > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > index cf15a350..9d675b3 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > @@ -873,9 +873,15 @@ static void > gfx_v9_0_compute_queue_acquire(struct amdgpu_device *adev) > > if (mec >= adev->gfx.mec.num_mec) > > break; > > > > - /* policy: amdgpu owns the first two queues of the first MEC > */ > > - if (mec == 0 && queue < 2) > > - set_bit(i, adev->gfx.mec.queue_bitmap); > > + if (adev->gfx.mec.num_mec > 1) { > > + /* policy: amdgpu owns the first two queues of the > first MEC */ > > + if (mec == 0 && queue < 2) > > + set_bit(i, adev->gfx.mec.queue_bitmap); > > + } else { > > + /* policy: amdgpu owns all queues in the first pipe */ > > + if (mec == 0 && pipe == 0) > > + set_bit(i, adev->gfx.mec.queue_bitmap); > > + } > > } > > > > /* update the number of active compute rings */ </div> </blockquote> </body> </html>