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<p>Reviewed-by: Alex Xie <a class="moz-txt-link-rfc2396E"
href="mailto:AlexBin.Xie@amd.com"><AlexBin.Xie@amd.com></a></p>
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<div class="moz-cite-prefix">On 2017-06-07 11:10 AM, Alex Deucher
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:1496848229-12761-3-git-send-email-alexander.deucher@amd.com">
<pre wrap="">This was missed when Andres' queue patches were rebased.
Fixes: 42794b27 (drm/amdgpu: take ownership of per-pipe configuration v3)
Signed-off-by: Alex Deucher <a class="moz-txt-link-rfc2396E" href="mailto:alexander.deucher@amd.com"><alexander.deucher@amd.com></a>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3ea0e71..e0193e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -872,6 +872,7 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_VEGA10:
+ case CHIP_RAVEN:
adev->gfx.mec.num_mec = 2;
break;
default:
</pre>
</blockquote>
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