<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> <meta name="Generator" content="Microsoft Exchange Server"> <style></style> </head> <body> <meta content="text/html; charset=UTF-8"> <style type="text/css" style="">  </style> <div dir="ltr"> <div id="x_divtagdefaultwrapper" dir="ltr" style="font-size:12pt; color:#000000; font-family:Calibri,Helvetica,sans-serif"> <p>Hi Shaoyun <br> </p> <p><br> </p> <p>looks you want to make KIQ reg access be atomic & UN-interruptible,</p> <p>I think most user of KIQ reg access is not in atomic context, so your patch only benefit for the place using KIQ from IRQ.</p> <p>why not implement another KIQ reg access function ? e.g. :<br> </p> <div style="color:#d4d4d4; background-color:#1e1e1e; font-family:'Droid Sans Mono','Courier New',monospace,'Droid Sans Fallback'; font-weight:normal; font-size:14px; line-height:19px; white-space:pre"> <div><span style="color:#dcdcaa">amdgpu_virt_kiq_rreg_atomic(...);<br> <span style="color:#dcdcaa">amdgpu_virt_kiq_wreg_atomic(...)</span>;</span><br> </div> </div> <p></p> <p><br> </p> <p>that way you can satisfy your requirement and not introduce unknown issue for other places that calling original virt_kiq_r/weg() function.</p> <p><br> </p> <p>because busy polling have chance to hang cpu in SR-IOV (imagine 16 VF, and many VF doing FLR one by one, your busy polling may let guest kernel cpu stuck in ATOMIC_CONTEXT for more than 5 seconds )<br> </p> <p><br> </p> <p>BR Monk<br> </p> </div> <hr tabindex="-1" style="display:inline-block; width:98%"> <div id="x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Liu, Shaoyun <Shaoyun.Liu@amd.com><br> <b>Sent:</b> Friday, June 30, 2017 10:55:39 PM<br> <b>To:</b> Christian König; Michel Dänzer<br> <b>Cc:</b> amd-gfx@lists.freedesktop.org<br> <b>Subject:</b> RE: [PATCH] drm/amdgpu: Make KIQ read/write register routine be atomic</font> <div> </div> </div> </div> <font size="2"><span style="font-size:10pt;"> <div class="PlainText">Hi , Christian<br> The new code actually will not use the fence function , it just need a memory that expose both CPU and GPU address . Do you really want to add the wrap functions that just expose the CPU and GPU address in this case ?<br> <br> Regards<br> Shaoyun.liu<br> <br> <br> -----Original Message-----<br> From: Christian König [<a href="mailto:deathsimple@vodafone.de">mailto:deathsimple@vodafone.de</a>] <br> Sent: Friday, June 30, 2017 3:57 AM<br> To: Michel Dänzer; Liu, Shaoyun<br> Cc: amd-gfx@lists.freedesktop.org<br> Subject: Re: [PATCH] drm/amdgpu: Make KIQ read/write register routine be atomic<br> <br> Am 30.06.2017 um 03:21 schrieb Michel Dänzer:<br> > On 30/06/17 06:08 AM, Shaoyun Liu wrote:<br> >> 1. Use spin lock instead of mutex in KIQ 2. Directly write to KIQ <br> >> fence address instead of using fence_emit() 3. Disable the interrupt <br> >> for KIQ read/write and use CPU polling<br> > This list indicates that this patch should be split up in at least <br> > three patches. :)<br> Yeah, apart from that is is not a good idea to mess with the fence internals directly in the KIQ code, please add a helper in the fence code for this.<br> <br> Regards,<br> Christian.<br> _______________________________________________<br> amd-gfx mailing list<br> amd-gfx@lists.freedesktop.org<br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br> </div> </span></font> </body> </html>