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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Christian König <ckoenig.leichtzumerken@gmail.com><br>
<b>Sent:</b> Wednesday, January 17, 2018 7:42 AM<br>
<b>To:</b> Alex Deucher<br>
<b>Cc:</b> amd-gfx list<br>
<b>Subject:</b> Re: [PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6</font>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">Am 16.01.2018 um 21:01 schrieb Alex Deucher:<br>
> On Tue, Jan 16, 2018 at 2:40 PM, Christian König<br>
> <ckoenig.leichtzumerken@gmail.com> wrote:<br>
>> Needed for vm_flush unification.<br>
>><br>
>> Signed-off-by: Christian König <christian.koenig@amd.com><br>
>> ---<br>
>> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12 ++++++++++++<br>
>> 1 file changed, 12 insertions(+)<br>
>><br>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c<br>
>> index c6e22eff89e7..b48b843c66ae 100644<br>
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c<br>
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c<br>
>> @@ -1059,6 +1059,17 @@ static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,<br>
>> amdgpu_ring_write(ring, ib->length_dw);<br>
>> }<br>
>><br>
>> +static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,<br>
>> + uint32_t reg, uint32_t val)<br>
>> +{<br>
>> + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));<br>
>> + amdgpu_ring_write(ring, reg << 2);<br>
>> + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));<br>
>> + amdgpu_ring_write(ring, val);<br>
>> + amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));<br>
>> + amdgpu_ring_write(ring, 0x8);<br>
> Is this valid on UVD6?<br>
<br>
This is valid on the decode ring of UVD6, only the HEVC UVD6 encode and <br>
VCE3 rings use different commands.<br>
<br>
> I think this may be a UVD7 thing. Looking at<br>
> the other UVD code, I think we just want:<br>
> amdgpu_ring_write(ring, PACKET0(reg, 0));<br>
> amdgpu_ring_write(ring, val);<br>
<br>
IIRC that won't work. The UVD RBC can only write to UVD registers using <br>
the PACKET0 command.</div>
<div class="PlainText"><br>
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<div class="PlainText">We probably need to fix a bunch of functions in uvd4,5,6,7 in that case which use packet0 directly to write non-UVD registers.<br>
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<div class="PlainText"><br>
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<div class="PlainText">Alex<br>
</div>
<div class="PlainText"><br>
<br>
Regards,<br>
Christian.<br>
<br>
><br>
> Alex<br>
><br>
><br>
>> +}<br>
>> +<br>
>> static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,<br>
>> unsigned vmid, unsigned pasid,<br>
>> uint64_t pd_addr)<br>
>> @@ -1595,6 +1606,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {<br>
>> .pad_ib = amdgpu_ring_generic_pad_ib,<br>
>> .begin_use = amdgpu_uvd_ring_begin_use,<br>
>> .end_use = amdgpu_uvd_ring_end_use,<br>
>> + .emit_wreg = uvd_v6_0_ring_emit_wreg,<br>
>> };<br>
>><br>
>> static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {<br>
>> --<br>
>> 2.14.1<br>
>><br>
>> _______________________________________________<br>
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>> amd-gfx@lists.freedesktop.org<br>
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