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<p style="margin-top:0;margin-bottom:0">Patches 1-4:</p>
<p style="margin-top:0;margin-bottom:0">Reviewed-by: Alex Deucher <alexander.deucher@amd.com></p>
<p style="margin-top:0;margin-bottom:0"><br>
</p>
<p style="margin-top:0;margin-bottom:0">patch 5:</p>
<p style="margin-top:0;margin-bottom:0">Is there a reason why you added a CURRENT field? <span>This should be consistent with vega10.
</span>Also, please add an AUTO profile for both asics to support dynamic driver controlled profile selection so the API is in place even if it's not hooked up yet.</p>
<p style="margin-top:0;margin-bottom:0"><br>
</p>
<p style="margin-top:0;margin-bottom:0">Alex<br>
</p>
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<hr style="display:inline-block;width:98%" tabindex="-1">
<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Rex Zhu <Rex.Zhu@amd.com><br>
<b>Sent:</b> Tuesday, January 23, 2018 5:05:02 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Zhu, Rex<br>
<b>Subject:</b> [PATCH 5/5] drm/amd/pp: Implement get_power_profile_mode on smu7</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">User can get smu7 profile pamameters through sysfs<br>
<br>
cat pp_power_profile_mode<br>
NUM MODE_NAME SCLK_UP_HYST SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL MCLK_UP_HYST MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL<br>
0 3D_FULL_SCREEN: 0 100 30 0 100 10<br>
1 POWER_SAVING: 10 0 30 * * *<br>
2 VIDEO: * * * 10 16 31<br>
3 VR: 0 11 50 0 100 10<br>
4 COMPUTE: 0 5 30 * * *<br>
5 CUSTOM: 0 0 0 0 0 0<br>
* CURRENT: 0 100 30 0 100 10<br>
<br>
Change-Id: I10e02f9e5fcd8e2b62c0cad620d9635336ea01dd<br>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com><br>
---<br>
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 94 ++++++++++++++++++++++++<br>
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h | 1 +<br>
2 files changed, 95 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
index f6236f9..7d68e23 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
@@ -81,6 +81,21 @@<br>
#define PCIE_BUS_CLK 10000<br>
#define TCLK (PCIE_BUS_CLK / 10)<br>
<br>
+static const struct profile_mode_setting smu7_profiling[5] =<br>
+ {{1, 0, 100, 30, 1, 0, 100, 10},<br>
+ {1, 10, 0, 30, 0, 0, 0, 0},<br>
+ {0, 0, 0, 0, 1, 10, 16, 31},<br>
+ {1, 0, 11, 50, 1, 0, 100, 10},<br>
+ {1, 0, 5, 30, 0, 0, 0, 0},<br>
+ };<br>
+<br>
+static const struct profile_mode_setting polaris11_profiling[5] =<br>
+ {{1, 0, 100, 30, 1, 0, 100, 10},<br>
+ {1, 10, 0, 30, 0, 0, 0, 0},<br>
+ {0, 0, 0, 0, 1, 10, 16, 62},<br>
+ {1, 0, 11, 50, 1, 0, 100, 10},<br>
+ {1, 0, 5, 30, 0, 0, 0, 0},<br>
+ };<br>
<br>
/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */<br>
enum DPM_EVENT_SRC {<br>
@@ -4934,6 +4949,83 @@ static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,<br>
return 0;<br>
}<br>
<br>
+static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)<br>
+{<br>
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);<br>
+ uint32_t i, size = 0;<br>
+ uint32_t len;<br>
+<br>
+ static const char *profile_name[6] = {"3D_FULL_SCREEN",<br>
+ "POWER_SAVING",<br>
+ "VIDEO",<br>
+ "VR",<br>
+ "COMPUTE",<br>
+ "CUSTOM"};<br>
+<br>
+ static const char *title[8] = {"NUM",<br>
+ "MODE_NAME",<br>
+ "SCLK_UP_HYST",<br>
+ "SCLK_DOWN_HYST",<br>
+ "SCLK_ACTIVE_LEVEL",<br>
+ "MCLK_UP_HYST",<br>
+ "MCLK_DOWN_HYST",<br>
+ "MCLK_ACTIVE_LEVEL"};<br>
+<br>
+ if (!buf)<br>
+ return -EINVAL;<br>
+<br>
+ size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n",<br>
+ title[0], title[1], title[2], title[3],<br>
+ title[4], title[5], title[6], title[7]);<br>
+<br>
+ len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);<br>
+<br>
+ for (i = 0; i < len; i++) {<br>
+ if (smu7_profiling[i].bupdate_sclk)<br>
+ size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",<br>
+ i, profile_name[i], smu7_profiling[i].sclk_up_hyst,<br>
+ smu7_profiling[i].sclk_down_hyst,<br>
+ smu7_profiling[i].sclk_activity);<br>
+ else<br>
+ size += sprintf(buf + size, "%3d %16s: %8s %16s %16s ",<br>
+ i, profile_name[i], "*", "*", "*");<br>
+<br>
+ if (smu7_profiling[i].bupdate_mclk)<br>
+ size += sprintf(buf + size, "%16d %16d %16d\n",<br>
+ smu7_profiling[i].mclk_up_hyst,<br>
+ smu7_profiling[i].mclk_down_hyst,<br>
+ smu7_profiling[i].mclk_activity);<br>
+ else<br>
+ size += sprintf(buf + size, "%16s %16s %16s\n",<br>
+ "*", "*", "*");<br>
+ }<br>
+<br>
+ size += sprintf(buf + size, "%3d %16s: %8d %16d %16d %16d %16d %16d\n",<br>
+ i, profile_name[i],<br>
+ data->custom_profile_setting.sclk_up_hyst,<br>
+ data->custom_profile_setting.sclk_down_hyst,<br>
+ data->custom_profile_setting.sclk_activity,<br>
+ data->custom_profile_setting.mclk_up_hyst,<br>
+ data->custom_profile_setting.mclk_down_hyst,<br>
+ data->custom_profile_setting.mclk_activity);<br>
+<br>
+ size += sprintf(buf + size, "%3s %16s: %8d %16d %16d %16d %16d %16d\n",<br>
+ "*", "CURRENT",<br>
+ data->current_profile_setting.sclk_up_hyst,<br>
+ data->current_profile_setting.sclk_down_hyst,<br>
+ data->current_profile_setting.sclk_activity,<br>
+ data->current_profile_setting.mclk_up_hyst,<br>
+ data->current_profile_setting.mclk_down_hyst,<br>
+ data->current_profile_setting.mclk_activity);<br>
+<br>
+ return size;<br>
+}<br>
+<br>
+static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)<br>
+{<br>
+ /* To Do */<br>
+ return 0;<br>
+}<br>
<br>
static const struct pp_hwmgr_func smu7_hwmgr_funcs = {<br>
.backend_init = &smu7_hwmgr_backend_init,<br>
@@ -4990,6 +5082,8 @@ static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,<br>
.get_max_high_clocks = smu7_get_max_high_clocks,<br>
.get_thermal_temperature_range = smu7_get_thermal_temperature_range,<br>
.odn_edit_dpm_table = smu7_odn_edit_dpm_table,<br>
+ .get_power_profile_mode = smu7_get_power_profile_mode,<br>
+ .set_power_profile_mode = smu7_set_power_profile_mode,<br>
};<br>
<br>
uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,<br>
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h<br>
index 3bcfc61..51aa4b3 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h<br>
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h<br>
@@ -327,6 +327,7 @@ struct smu7_hwmgr {<br>
uint32_t vr_config;<br>
struct profile_mode_setting custom_profile_setting;<br>
struct profile_mode_setting current_profile_setting;<br>
+ enum PP_SMC_POWER_PROFILE profile_mode;<br>
};<br>
<br>
/* To convert to Q8.8 format for firmware */<br>
-- <br>
1.9.1<br>
<br>
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