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Hi Felix,<br>
<br>
The logic of gfx/computer profile setting works in such way as you said,need under “auto” state.<br>
But in new sysfs of power profile setting, we do not check the performance<br>
Level.<br>
<br>
And The “manual” state is a confusing flag,when user set manual state,and then change the clk range through pp-dpm-sclk/mclk,the dpm still works automatically in new clock range, I think we can remove this flag.<br>
<br>
So  My idea is <br>
in the sysfs of pp dpm sclk/mclk, user can set clock range.<br>
In the sysfs of power profile state, user can configure the parameters smu/driver exposed. They are independent.<br>
<br>
<br>
<br>
<br>
<br>
<br>
Best Regards<br>
Rex
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Kuehling, Felix<br>
<b>Sent:</b> Thursday, January 25, 2018 5:41:43 AM<br>
<b>To:</b> Zhu, Rex; Huang, JinHuiEric; amd-gfx@lists.freedesktop.org<br>
<b>Subject:</b> Re: [PATCH 4/4] drm/amd/pp: Implement set_power_profile_mode on smu7</font>
<div> </div>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">Hi Rex,<br>
<br>
As I understand it (the way power profiles currently work),<br>
pp_dpm_sclk/mclk only apply if pp_dpm_force_performance_level is set to<br>
"manual". Power profiles and automatic switching between profiles only<br>
happens when pp_dpm_force_performance_level is set to "auto".<br>
<br>
This means pp_dpm_sclk/mclk don't apply when profiles are in effect.<br>
Also, there would be no way to set different minimum clocks for<br>
different profiles.<br>
<br>
I think minimum clocks should be part of the profiles.<br>
<br>
Regards,<br>
  Felix<br>
<br>
<br>
On 2018-01-24 03:13 PM, Zhu, Rex wrote:<br>
> Hi Eric,<br>
><br>
> We have sysfs pp-dpm-sclk/mclk to set min dpm level<br>
><br>
> Best Regards<br>
> Rex<br>
> ------------------------------------------------------------------------<br>
> *From:* amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of<br>
> Eric Huang <jinhuieric.huang@amd.com><br>
> *Sent:* Thursday, January 25, 2018 12:04:55 AM<br>
> *To:* amd-gfx@lists.freedesktop.org<br>
> *Subject:* Re: [PATCH 4/4] drm/amd/pp: Implement<br>
> set_power_profile_mode on smu7<br>
>  <br>
> We have min_sclk and min_mclk in previous power profile parameters for<br>
> VI, which are similar with min_active_level for Vega10. How to implement<br>
> these parameters?<br>
><br>
> Regards,<br>
> Eric<br>
><br>
> On 2018-01-24 04:37 AM, Rex Zhu wrote:<br>
> > User can set smu7 profile pamameters through sysfs<br>
> ><br>
> > echo "0/1/2/3/4">pp_power_profile_mode<br>
> > to select 3D_FULL_SCREEN/POWER_SAVING/VIDEO/VR/COMPUTE<br>
> > mode.<br>
> > echo "5 * * * * * * * *">pp_power_profile_mode<br>
> > to config custom mode.<br>
> > "5 * * * * * * * *" mean "CUSTOM enable_sclk SCLK_UP_HYST<br>
> > SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL enable_mclk MCLK_UP_HYST<br>
> > MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL"<br>
> ><br>
> > Change-Id: Ic6d6f37363bc81ab17051285f6ace847edf725de<br>
> > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com><br>
> > ---<br>
> >   drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 49<br>
> +++++++++++++++++++++++-<br>
> >   1 file changed, 48 insertions(+), 1 deletion(-)<br>
> ><br>
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
> > index 9f6afd5..13db75c 100644<br>
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
> > @@ -5036,7 +5036,54 @@ static int smu7_get_power_profile_mode(struct<br>
> pp_hwmgr *hwmgr, char *buf)<br>
> >  <br>
> >   static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr,<br>
> long *input, uint32_t size)<br>
> >   {<br>
> > -     /* To Do */<br>
> > +     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);<br>
> > +     struct profile_mode_setting tmp;<br>
> > +<br>
> > +     hwmgr->power_profile_mode = input[size];<br>
> > +<br>
> > +     switch (hwmgr->power_profile_mode) {<br>
> > +     case PP_SMC_POWER_PROFILE_CUSTOM:<br>
> > +             if (size < 8)<br>
> > +                     return -EINVAL;<br>
> > +<br>
> > +             data->custom_profile_setting.bupdate_sclk = input[0];<br>
> > +             data->custom_profile_setting.sclk_up_hyst = input[1];<br>
> > +             data->custom_profile_setting.sclk_down_hyst = input[2];<br>
> > +             data->custom_profile_setting.sclk_activity =  input[3];<br>
> > +             data->custom_profile_setting.bupdate_mclk = input[4];<br>
> > +             data->custom_profile_setting.mclk_up_hyst = input[5];<br>
> > +             data->custom_profile_setting.mclk_down_hyst = input[6];<br>
> > +             data->custom_profile_setting.mclk_activity =  input[7];<br>
> > +             if (!smum_update_dpm_settings(hwmgr,<br>
> &data->custom_profile_setting))<br>
> > +                     memcpy(&data->current_profile_setting,<br>
> &data->custom_profile_setting, sizeof(struct profile_mode_setting));<br>
> > +             break;<br>
> > +     case PP_SMC_POWER_PROFILE_FULLSCREEN3D:<br>
> > +     case PP_SMC_POWER_PROFILE_POWERSAVING:<br>
> > +     case PP_SMC_POWER_PROFILE_VIDEO:<br>
> > +     case PP_SMC_POWER_PROFILE_VR:<br>
> > +     case PP_SMC_POWER_PROFILE_COMPUTE:<br>
> > +             memcpy(&tmp,<br>
> &smu7_profiling[hwmgr->power_profile_mode], sizeof(struct<br>
> profile_mode_setting));<br>
> > +             if (!smum_update_dpm_settings(hwmgr, &tmp)) {<br>
> > +                     if (tmp.bupdate_sclk) {<br>
> > +                            <br>
> data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;<br>
> > +                            <br>
> data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;<br>
> > +                            <br>
> data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;<br>
> > +                            <br>
> data->current_profile_setting.sclk_activity = tmp.sclk_activity;<br>
> > +                     }<br>
> > +                     if (tmp.bupdate_mclk) {<br>
> > +                            <br>
> data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;<br>
> > +                            <br>
> data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;<br>
> > +                            <br>
> data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;<br>
> > +                            <br>
> data->current_profile_setting.mclk_activity = tmp.mclk_activity;<br>
> > +                     }<br>
> > +             }<br>
> > +             break;<br>
> > +     case PP_SMC_POWER_PROFILE_AUTO: /* TO DO auto wattman feature<br>
> not implement */<br>
> > +             return 0;<br>
> > +     default:<br>
> > +             return -EINVAL;<br>
> > +     }<br>
> > +<br>
> >        return 0;<br>
> >   }<br>
> >  <br>
><br>
> _______________________________________________<br>
> amd-gfx mailing list<br>
> amd-gfx@lists.freedesktop.org<br>
> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br>
><br>
><br>
> _______________________________________________<br>
> amd-gfx mailing list<br>
> amd-gfx@lists.freedesktop.org<br>
> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br>
<br>
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