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<p style="margin-top:0;margin-bottom:0">Please provide a better message body.  E.g.,</p>
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<p style="margin-top:0;margin-bottom:0">Lock the dpm levels when we modify the dpm tables to avoid a possible race with the smu.</p>
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<p style="margin-top:0;margin-bottom:0">With that:</p>
<p style="margin-top:0;margin-bottom:0">Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Rex Zhu <Rex.Zhu@amd.com><br>
<b>Sent:</b> Friday, February 9, 2018 3:49 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Zhu, Rex<br>
<b>Subject:</b> [PATCH] drm/amd/pp: Fix bug not sync with firmware when update pptable</font>
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<div class="PlainText">Change-Id: Ibb250af8a8cf2af0c30acbad16a354ed0dffa130<br>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com><br>
---<br>
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 22 ++++++++++++++--------<br>
 1 file changed, 14 insertions(+), 8 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
index 79a14de..5c1e445 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
@@ -4689,20 +4689,26 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,<br>
         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)<br>
                 return -EINVAL;<br>
 <br>
-       tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);<br>
-       PP_ASSERT_WITH_CODE(!tmp_result,<br>
-                       "Failed to freeze SCLK MCLK DPM!",<br>
-                       result = tmp_result);<br>
+       if (smum_is_dpm_running(hwmgr) {<br>
+               if (!data->sclk_dpm_key_disabled )<br>
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel);<br>
+<br>
+               if (!data->mclk_dpm_key_disabled)<br>
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel);<br>
+       }<br>
 <br>
         tmp_result = smum_populate_requested_graphic_levels(hwmgr, request);<br>
         PP_ASSERT_WITH_CODE(!tmp_result,<br>
                         "Failed to populate requested graphic levels!",<br>
                         result = tmp_result);<br>
 <br>
-       tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);<br>
-       PP_ASSERT_WITH_CODE(!tmp_result,<br>
-                       "Failed to unfreeze SCLK MCLK DPM!",<br>
-                       result = tmp_result);<br>
+       if (smum_is_dpm_running(hwmgr) {<br>
+               if (!data->sclk_dpm_key_disabled )<br>
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel);<br>
+<br>
+               if (!data->mclk_dpm_key_disabled)<br>
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel);<br>
+       }<br>
 <br>
         smu7_find_min_clock_masks(hwmgr, &sclk_mask, &mclk_mask,<br>
                         request->min_sclk, request->min_mclk);<br>
-- <br>
1.9.1<br>
<br>
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