<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> <style type="text/css" style="display:none;"></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size: 12pt; color: rgb(0, 0, 0); font-family: Calibri, Helvetica, sans-serif, "EmojiFont", "Apple Color Emoji", "Segoe UI Emoji", NotoColorEmoji, "Segoe UI Symbol", "Android Emoji", EmojiSymbols;" dir="ltr"> <p style="margin-top:0;margin-bottom:0">Acked-by: Alex Deucher <alexander.deucher@amd.com><br> </p> <div style="color: rgb(0, 0, 0);"> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Eric Huang <JinHuiEric.Huang@amd.com><br> <b>Sent:</b> Thursday, February 22, 2018 1:21 PM<br> <b>To:</b> amd-gfx@lists.freedesktop.org<br> <b>Cc:</b> Huang, JinHuiEric<br> <b>Subject:</b> [PATCH] drm/amd/powerplay: fix thermal interrupts on vega10</font> <div> </div> </div> <div class="BodyFragment"><font size="2"><span style="font-size:11pt;"> <div class="PlainText">a bug in programming thermal interrupt register masks out<br> interrupts and driver cannot receive interrupts. Setting<br> 0 to mask bits will fix it.<br> <br> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com><br> ---<br> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 4 +++-<br> 1 file changed, 3 insertions(+), 1 deletion(-)<br> <br> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c<br> index 7491163..eb6e965 100644<br> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c<br> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c<br> @@ -409,7 +409,9 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,<br> val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);<br> val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));<br> val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));<br> - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);<br> + val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &<br> + (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &<br> + (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);<br> <br> cgs_write_register(hwmgr->device, reg, val);<br> <br> -- <br> 2.7.4<br> <br> _______________________________________________<br> amd-gfx mailing list<br> amd-gfx@lists.freedesktop.org<br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx" id="LPlnk875302" previewremoved="true">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br> </div> </span></font></div> </div> </div> </body> </html>