<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> <style type="text/css" style="display:none;"></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size: 12pt; color: rgb(0, 0, 0); font-family: Calibri, Helvetica, sans-serif, "EmojiFont", "Apple Color Emoji", "Segoe UI Emoji", NotoColorEmoji, "Segoe UI Symbol", "Android Emoji", EmojiSymbols;" dir="ltr"> <p style="margin-top:0;margin-bottom:0">Acked-by: Alex Deucher <alexander.deucher@amd.com><br> </p> <div style="color: rgb(0, 0, 0);"> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Emily Deng <Emily.Deng@amd.com><br> <b>Sent:</b> Monday, March 5, 2018 9:14 PM<br> <b>To:</b> amd-gfx@lists.freedesktop.org<br> <b>Cc:</b> Deng, Emily<br> <b>Subject:</b> [PATCH] drm/amdgpu: Disable sdma wptr polling memory for sriov</font> <div> </div> </div> <div class="BodyFragment"><font size="2"><span style="font-size:11pt;"> <div class="PlainText">The sdma wptr polling memory will introduce serious issue sdma hang for<br> sriov environment on sdma v3.<br> And the sdma wptr polling memory is only to fix the FLR cornner case, the<br> issue's probabity is very low.<br> <br> Change-Id: I2c447533aac6b16d541f58644d141228dd75dfb3<br> Signed-off-by: Emily Deng <Emily.Deng@amd.com><br> ---<br> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +----<br> 1 file changed, 1 insertion(+), 4 deletions(-)<br> <br> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c<br> index ec885ff..44d7d08 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c<br> @@ -716,10 +716,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)<br> WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],<br> upper_32_bits(wptr_gpu_addr));<br> wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);<br> - if (amdgpu_sriov_vf(adev))<br> - wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);<br> - else<br> - wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);<br> + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);<br> WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);<br> <br> /* enable DMA RB */<br> -- <br> 2.7.4<br> <br> _______________________________________________<br> amd-gfx mailing list<br> amd-gfx@lists.freedesktop.org<br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx" id="LPlnk353796" previewremoved="true">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br> </div> </span></font></div> </div> </div> </body> </html>