<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> </head> <body text="#000000" bgcolor="#FFFFFF"> <div class="moz-cite-prefix"> <blockquote type="cite">Although KMD now use a cache way to give libdrm the CC_RB_BACKEND_DISABLE value, but KMD still need to read it at least one shot during loading driver right ?</blockquote> Correct, but we do this while having exclusive access. <blockquote type="cite">Not only tlb flush, other ring’s vm flush of VF2 can all be ruined by this register’s reading from VF1, right ?</blockquote> Not sure about that. But as I said that problem is not limited to VM flushes, e.g. when you access this register any other register write or read can be affected. May theory is that accessing those registers sometimes times out when the MC is to busy or something like this and this timeout in turn results in a register bus reset which affects all other ongoing operations as well. <blockquote type="cite"> How you solve that ? </blockquote> Stop accessing the affected registers as much as possible, there is no really any other known workaround. The risk by accessing it when the driver loads is minimal, we just need to make sure that we don't touch them during world switch. Regards, Christian. Am 08.03.2018 um 11:11 schrieb Liu, Monk: </div> <blockquote type="cite" cite="mid:BLUPR12MB044982457323EEB3BFC1E39E84DF0@BLUPR12MB0449.namprd12.prod.outlook.com"> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)">  <style></style> <div class="WordSection1"> To be more specific let me give you an example we face with now:<o:p></o:p> <o:p> </o:p> Although KMD now use a cache way to give libdrm the CC_RB_BACKEND_DISABLE value, but KMD still need to read it at least one shot during loading driver right ?<o:p></o:p> For SR-IOV there is still chance that VF2 is doing CPU based tlb flush while VF1 is doing driver loading, so there are chance that tlb flush of VF2 was ruined by <o:p></o:p> The driver loading (one shot CC_RB_BACKEND_DISABLE reading).<o:p></o:p> <o:p> </o:p> Not only tlb flush, other ring’s vm flush of VF2 can all be ruined by this register’s reading from VF1, right ?<o:p></o:p> <o:p> </o:p> How you solve that ?<o:p></o:p> <o:p> </o:p> /Monk<o:p></o:p> <o:p> </o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm"> From: amd-gfx [<a class="moz-txt-link-freetext" href="mailto:amd-gfx-bounces@lists.freedesktop.org">mailto:amd-gfx-bounces@lists.freedesktop.org</a>] On Behalf Of Liu, Monk Sent: 2018年3月8日 18:03 To: Koenig, Christian <a class="moz-txt-link-rfc2396E" href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a>; Deucher, Alexander <a class="moz-txt-link-rfc2396E" href="mailto:Alexander.Deucher@amd.com"><Alexander.Deucher@amd.com></a>; Mao, David <a class="moz-txt-link-rfc2396E" href="mailto:David.Mao@amd.com"><David.Mao@amd.com></a> Cc: Jin, Jian-Rong <a class="moz-txt-link-rfc2396E" href="mailto:Jian-Rong.Jin@amd.com"><Jian-Rong.Jin@amd.com></a>; <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> Subject: RE: deprecated register issues<o:p></o:p> </div> </div> <o:p> </o:p> Yeah, I agree with you we’d better find all those registers<o:p></o:p> <o:p> </o:p> Stitch together the REQ and ACK part only avoid this issue for vm flush only, and we may still hit the issue in other place, I knew it.<o:p></o:p> <o:p> </o:p> The frustrating job is how can we find all those registers ?<o:p></o:p> And more is since this CC_RB_BACKEND_DISABLE register is not deprecated (confirmed with David M), and driver indeed nee to read it<o:p></o:p> How could we avoid this reading cause vm hub broken ?<o:p></o:p> <o:p> </o:p> I believe like you said there are a bunch of registers (not really deprecated ) reading would cause vm hub broken, how could we still read<o:p></o:p> Them when we want but also not to trigger the world switch issue ? <o:p></o:p> <o:p> </o:p> looks to me there is no way to do that, even if you already find out all of those registers, we still need to access them, so the world switch (or other issues)<o:p></o:p> are still going to fail, and that’s why I think the plan B at least have its reason to stand there.<o:p></o:p> <o:p> </o:p> any thought ?<o:p></o:p> /Monk<o:p></o:p> <o:p> </o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm"> From: Christian König [<a href="mailto:ckoenig.leichtzumerken@gmail.com" moz-do-not-send="true">mailto:ckoenig.leichtzumerken@gmail.com</a>] Sent: 2018年3月8日 17:41 To: Liu, Monk <<a href="mailto:Monk.Liu@amd.com" moz-do-not-send="true">Monk.Liu@amd.com</a>>; Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com" moz-do-not-send="true">Alexander.Deucher@amd.com</a>>; Koenig, Christian <<a href="mailto:Christian.Koenig@amd.com" moz-do-not-send="true">Christian.Koenig@amd.com</a>>; Mao, David <<a href="mailto:David.Mao@amd.com" moz-do-not-send="true">David.Mao@amd.com</a>> Cc: Jin, Jian-Rong <<a href="mailto:Jian-Rong.Jin@amd.com" moz-do-not-send="true">Jian-Rong.Jin@amd.com</a>>; <a href="mailto:amd-gfx@lists.freedesktop.org" moz-do-not-send="true">amd-gfx@lists.freedesktop.org</a> Subject: Re: deprecated register issues<o:p></o:p> </div> </div> <o:p> </o:p> <div> Hi Monk, <o:p></o:p> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> While we can avoid such vm flush failure by stitch together of the sending REQ and reading ACK part, at least for compute ring this is confirmed.<o:p></o:p> </blockquote> Well there are two misunderstanding here. First of all this solution doesn't really work, it just hides the problem because we don't do a world switch in between those two packets any more. And while we could change the SDMA, UVD and VCE firmware do to something similar you can't apply this solution to CPU based flushes. The second issue is that this isn't related to VMHUB flushing at all, it's just that VMHUB flushing is the first thing where you notice that something is wrong. The real problem is that when you access CC_RB_BACKEND_DISABLE and a bunch of other registers the bus on Vega10 sometimes gets a hickup and drops other reads and writes. So we need to identify those registers and removes all accesses to them, otherwise working with the hardware will just be horrible unreliable in general. Regards, Christian. Am 08.03.2018 um 04:05 schrieb Liu, Monk:<o:p></o:p> </div> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> Hi Alex<o:p></o:p> <o:p></o:p> While we can avoid such vm flush failure by stitch together of the sending REQ and reading ACK part, at least for compute ring this is confirmed.<o:p></o:p> And I believe for SDMA ring (even UVD/VCE ring) it could also be achieved.<o:p></o:p> <o:p></o:p> But <a id="OWAAM88494E83DC8949F581E2AEBF1FC603DA" href="mailto:Christian.Koenig@amd.com" moz-do-not-send="true"> @Koenig, Christian</a> insist stitching together the REQ AND ACK part is not a formal way to fix the issue, instead just a walkaround and I cannot debate that<o:p></o:p> <o:p></o:p> What make me worry more is what if there are more registers like Alex said that behaves like this CC_RB_BACKEND_DISABLE, <o:p></o:p> since we don’t know their names(too hard to filter them out!) so we couldn’t remove them all from SR list, <o:p></o:p> So I still think we need plan B to handle above case, A.K.A use one package for the REQ and ACK job<o:p></o:p> <o:p></o:p> /Monk<o:p></o:p> <o:p></o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm"> From: Deucher, Alexander Sent: 2018年3月8日 10:53 To: Liu, Monk <a href="mailto:Monk.Liu@amd.com" moz-do-not-send="true"><Monk.Liu@amd.com></a>; Koenig, Christian <a href="mailto:Christian.Koenig@amd.com" moz-do-not-send="true"><Christian.Koenig@amd.com></a>; Mao, David <a href="mailto:David.Mao@amd.com" moz-do-not-send="true"><David.Mao@amd.com></a> Cc: <a href="mailto:amd-gfx@lists.freedesktop.org" moz-do-not-send="true">amd-gfx@lists.freedesktop.org</a>; Jin, Jian-Rong <a href="mailto:Jian-Rong.Jin@amd.com" moz-do-not-send="true"><Jian-Rong.Jin@amd.com></a> Subject: Re: deprecated register issues<o:p></o:p> </div> </div> <o:p></o:p> <div id="divtagdefaultwrapper"> I think there are more than just CC_RB_BACKEND_DISABLE that could cause this problem. IIRC, some entire class of gfx registers could cause it, it just happened that this was one of the only ones we readback via mmio. Also for the save and restore list, I think the RLC uses a different interface to read back the registers so it may not be affected the same way.<o:p></o:p> <o:p></o:p> Alex<o:p></o:p> </div> <div class="MsoNormal" style="text-align:center" align="center"> <hr align="center" size="3" width="98%"> </div> <div id="divRplyFwdMsg"> From: Liu, Monk Sent: Wednesday, March 7, 2018 9:42:41 PM To: Deucher, Alexander; Koenig, Christian; Mao, David Cc: <a href="mailto:amd-gfx@lists.freedesktop.org" moz-do-not-send="true">amd-gfx@lists.freedesktop.org</a>; Jin, Jian-Rong Subject: RE: deprecated register issues <o:p></o:p> <div> <o:p></o:p> </div> </div> <div> <div> Hi guys <o:p></o:p> <o:p></o:p> According to Christian’s found, reading this register would make vm hub failed to finish the vm flush request , e.g.: sdma is doing vm flush which first write data to vm_invalidat_req and read result from vm_invalidate_ack, but found driver will forever failed to get the correct value from vm_invalidate_ack if the meantime BIF is reading this CC_RB_BACKEND_DISABLE register.<o:p></o:p> <o:p></o:p> Now SR-IOV world switch also may get such similar trouble, see below save_restore_list ( during world_switch, RLCV will save current VF’s register according to this list and restore all those registers when loading back this VF)<o:p></o:p> <o:p></o:p> uint32 register_restore[] = {<o:p></o:p> (uint32)((0x3000 << 18) | mmPA_SC_FIFO_SIZE), /* SC */<o:p></o:p> 0x00000001,<o:p></o:p> (uint32)((0x3000 << 18) | mmCC_RB_BACKEND_DISABLE), /* SC SC PER_SE */<o:p></o:p> 0x00000000,<o:p></o:p> (uint32)((0x3400 << 18) | mmCC_RB_BACKEND_DISABLE), /* SC SC PER_SE */<o:p></o:p> 0x00000000,<o:p></o:p> (uint32)((0x3800 << 18) | mmCC_RB_BACKEND_DISABLE), /* SC SC PER_SE */<o:p></o:p> 0x00000000,<o:p></o:p> (uint32)((0x3c00 << 18) | mmCC_RB_BACKEND_DISABLE), /* SC SC PER_SE */<o:p></o:p> 0x00000000,<o:p></o:p> (uint32)((0x3000 << 18) | mmVGT_VTX_VECT_EJECT_REG), <o:p></o:p> 0x00000001,<o:p></o:p> (uint32)((0x3000 << 18) | mmVGT_DMA_DATA_FIFO_DEPTH), /* IA WD */<o:p></o:p> 0x00000001,<o:p></o:p> (uint32)((0x3000 << 18) | mmVGT_DMA_REQ_FIFO_DEPTH), /* WD */<o:p></o:p> 0x00000001,<o:p></o:p> (uint32)((0x3000 << 18) | mmVGT_DRAW_INIT_FIFO_DEPTH), /* WD */<o:p></o:p> 0x00000001,<o:p></o:p> (uint32)((0x3000 << 18) | mmVGT_CACHE_INVALIDATION), /* IA */<o:p></o:p> 0x00000001,<o:p></o:p> (uint32)((0x3000 << 18) | mmVGT_RESET_DEBUG), /* WD */<o:p></o:p> 0x00000001,<o:p></o:p> (uint32)((0x3000 << 18) | mmVGT_FIFO_DEPTHS), <o:p></o:p> <o:p></o:p> I will do some test against this CC_RB_BACKEND_DISABLE register, see if vm flush failure issue could be avoided by removing those four register from SR list <o:p></o:p> <o:p></o:p> Thanks<o:p></o:p> <o:p></o:p> /Monk<o:p></o:p> <o:p></o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm"> From: Deucher, Alexander Sent: 2018年3月7日 23:13 To: Koenig, Christian <<a href="mailto:Christian.Koenig@amd.com" moz-do-not-send="true">Christian.Koenig@amd.com</a>>; Mao, David <<a href="mailto:David.Mao@amd.com" moz-do-not-send="true">David.Mao@amd.com</a>>; Liu, Monk <<a href="mailto:Monk.Liu@amd.com" moz-do-not-send="true">Monk.Liu@amd.com</a>> Cc: <a href="mailto:amd-gfx@lists.freedesktop.org" moz-do-not-send="true">amd-gfx@lists.freedesktop.org</a>; Jin, Jian-Rong <<a href="mailto:Jian-Rong.Jin@amd.com" moz-do-not-send="true">Jian-Rong.Jin@amd.com</a>> Subject: Re: deprecated register issues<o:p></o:p> </div> </div> <o:p></o:p> <div id="x_divtagdefaultwrapper"> Right. We ran into issues with reading back that register at runtime when UMDs queried it when other stuff was in flight, so we just read it once at startup and cache the results. Now when UMDs request it, we return the cached value.<o:p></o:p> <o:p></o:p> Alex<o:p></o:p> </div> <div class="MsoNormal" style="text-align:center" align="center"> <hr align="center" size="3" width="98%"> </div> <div id="x_divRplyFwdMsg"> From: Koenig, Christian Sent: Wednesday, March 7, 2018 9:31:13 AM To: Mao, David; Liu, Monk Cc: Deucher, Alexander; <a href="mailto:amd-gfx@lists.freedesktop.org" moz-do-not-send="true">amd-gfx@lists.freedesktop.org</a>; Jin, Jian-Rong Subject: Re: deprecated register issues <o:p></o:p> <div> <o:p></o:p> </div> </div> <div> <div> Hi David, well I just figured that this is a misunderstanding. Accessing this register and some other deprecated registers can cause problem when invalidating VMHUBs. This register itself isn't deprecated, the wording in a patch fixing things is just a bit unclear. Question is is that register still accessed regularly or is it value cached after startup? Regards, Christian. Am 07.03.2018 um 15:25 schrieb Mao, David:<o:p></o:p> </div> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> We requires base driver to provide the mask of disabled RB. <o:p></o:p> <div> This is why kernel read the CC_RB_BACKEND_DISABLE to collect the harvest configuration.<o:p></o:p> </div> <div> Where did you get to know that the register is deprecated?<o:p></o:p> </div> <div> I think it should still be there.<o:p></o:p> </div> <div> <o:p></o:p> </div> <div> Best Regards,<o:p></o:p> </div> <div> David<o:p></o:p> <div> <o:p></o:p> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> <div> On Mar 7, 2018, at 9:49 PM, Liu, Monk <<a href="mailto:Monk.Liu@amd.com" moz-do-not-send="true">Monk.Liu@amd.com</a>> wrote:<o:p></o:p> </div> <o:p></o:p> <div> <div> <div> + UMD guys<o:p></o:p> </div> <div> <o:p></o:p> </div> <div> Hi David<o:p></o:p> </div> <div> <o:p></o:p> </div> <div> Do you know if GC_USER_RB_BACKEND_DISABLE is still exist for gfx9/vega10 ?<o:p></o:p> </div> <div> <o:p></o:p> </div> <div> We found CC_RB_BACKEND_DISABLE was deprecated but looks it is still in use in kmd, so<o:p></o:p> </div> <div> I want to check with you both of above registers<o:p></o:p> </div> <div> <o:p></o:p> </div> <div> Thanks <o:p></o:p> </div> <div> /Monk<o:p></o:p> </div> <div> <o:p></o:p> </div> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm"> <div> From: amd-gfx [<a href="mailto:amd-gfx-bounces@lists.freedesktop.org" moz-do-not-send="true">mailto:amd-gfx-bounces@lists.freedesktop.org</a>] On Behalf Of Christian K?nig Sent: 2018年3月7日 20:26 To: Liu, Monk <<a href="mailto:Monk.Liu@amd.com" moz-do-not-send="true">Monk.Liu@amd.com</a>>; Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com" moz-do-not-send="true">Alexander.Deucher@amd.com</a>> Cc: <a href="mailto:amd-gfx@lists.freedesktop.org" moz-do-not-send="true">amd-gfx@lists.freedesktop.org</a> Subject: Re: deprecated register issues<o:p></o:p> </div> </div> </div> <div> <o:p></o:p> </div> <div> <div> Hi Monk, I honestly don't have the slightest idea why we are still accessing CC_RB_BACKEND_DISABLE. Maybe it still contains some useful values? Key point was that we needed to stop accessing it all the time to avoid triggering problems. Regards, Christian. Am 07.03.2018 um 13:11 schrieb Liu, Monk:<o:p></o:p> </div> </div> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> <div> Hi Christian<o:p></o:p> <o:p></o:p> I remember you and AlexD mentioned that a handful registers are deprecated for greenland (gfx9)<o:p></o:p> e.g. CC_RB_BACKEND_DISABLE<o:p></o:p> <o:p></o:p> do you know why we still have this routine ?<o:p></o:p> <div> <div> <o:p></o:p> </div> <div> <div> static u32<o:p></o:p> </div> <div> gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)<o:p></o:p> </div> </div> <div> <o:p></o:p> </div> <div> <div> {<o:p></o:p> </div> </div> <div> <o:p></o:p> </div> <div> <div> u32 data, mask;<o:p></o:p> </div> </div> <div> <o:p></o:p> </div> <div> <o:p></o:p> </div> <div> <o:p></o:p> </div> <div> <div> data = RREG32_SOC15(GC,<o:p></o:p> </div> <div> 0, mmCC_RB_BACKEND_DISABLE);<o:p></o:p> </div> </div> <div> <o:p></o:p> </div> <div> <div> data |= RREG32_SOC15(GC,<o:p></o:p> </div> <div> 0, mmGC_USER_RB_BACKEND_DISABLE);<o:p></o:p> </div> </div> <div> <o:p></o:p> </div> <div> <o:p></o:p> </div> <div> <o:p></o:p> </div> <div> <div> data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;<o:p></o:p> </div> </div> <div> <o:p></o:p> </div> <div> <div> data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;<o:p></o:p> </div> </div> <div> <o:p></o:p> </div> <div> <o:p></o:p> </div> <div> <o:p></o:p> </div> <div> <div> mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /<o:p></o:p> </div> </div> <div> <o:p></o:p> </div> <div> <div> adev->gfx.config.max_sh_per_se);<o:p></o:p> </div> </div> <div> <o:p></o:p> </div> <div> <o:p></o:p> </div> <div> <o:p></o:p> </div> <div> <div> return (~data) & mask;<o:p></o:p> </div> </div> <div> <o:p></o:p> </div> <div> <div> }<o:p></o:p> </div> </div> <div> <o:p></o:p> </div> </div> <div> <o:p></o:p> </div> see that it still read CC_RB_BACKEND_DISABLE<o:p></o:p> <o:p></o:p> thanks<o:p></o:p> <o:p></o:p> /Monk<o:p></o:p> <o:p></o:p> </div> </blockquote> <div> <o:p></o:p> </div> </div> </div> </blockquote> </div> <o:p></o:p> </div> </blockquote> <o:p></o:p> </div> </div> </div> <o:p></o:p> <pre>_______________________________________________<o:p></o:p></pre> <pre>amd-gfx mailing list<o:p></o:p></pre> <pre><a href="mailto:amd-gfx@lists.freedesktop.org" moz-do-not-send="true">amd-gfx@lists.freedesktop.org</a><o:p></o:p></pre> <pre><a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx" moz-do-not-send="true">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><o:p></o:p></pre> </blockquote> <o:p> </o:p> </div> </blockquote> </body> </html>