<div dir="ltr">I have the radeon driver working on the T2080, and am currently running into a problem with gallium/mesa. My problem was a mismatch<div>between u-boot and my device-tree that caused PCI Express to misbehave.<br><div><br></div><div>When I run a program calling OpenCL, I get a segfault. The cause for this particular crash in src/gallium/drivers/radeonsi/si_state_draw.c:474 </div><div>is the use of bit fields in union si_vgt_param_key (from src/gallium/drivers/radeonsi/si_pipe.h:310). I'm fairly sure there will be other instances.</div><div><br></div><div>Is there a best practice on resolving this? Point me in the right direction and I'll create some patches to get this fixed.</div><div><br></div><div>Bas Vermeulen</div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Feb 22, 2018 at 9:51 AM, Christian König <span dir="ltr"><<a href="mailto:christian.koenig@amd.com" target="_blank">christian.koenig@amd.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<div class="m_7914511615307514869moz-cite-prefix">Am 22.02.2018 um 09:37 schrieb Bas
Vermeulen:<br>
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<div class="gmail_extra">
<div class="gmail_quote"><span class="">On Wed, Feb 21, 2018 at 6:22 PM, Alex
Deucher <span dir="ltr"><<a href="mailto:alexdeucher@gmail.com" target="_blank">alexdeucher@gmail.com</a>></span>
wrote:<br>
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<div class="m_7914511615307514869gmail-h5"><span class="">On Wed, Feb 21, 2018 at 7:43 AM,
Christian König<br></span>
[SNIP]<span class=""><br>
> Apart from that I don't have any good idea any
more why that shouldn't work.<br>
<br>
</span></div>
</div><span class="">
Does your platform properly handle DMA masks? Most radeon
hw only<br>
supports a 40 bit DMA mask. If there are relevant bits in
the upper<br>
bits of the address, they will be lost when the hw tries
to use the<br>
address. On at least some powerpc hw, I believe there is
some memory<br>
routing related info in the high bits.<br>
</span></blockquote><span class="">
<div><br>
</div>
<div>On 4.1 (without the hashing algorithm when printing
pointers), The rings are placed thus:</div>
<div><br>
</div>
<div>
<div>[ 11.002673] radeon 0002:01:00.0: fence driver on
ring 0 use gpu addr 0x0000000080000c00 and cpu addr
0xc00000007c0c8c00</div>
<div>[ 11.012165] radeon 0002:01:00.0: fence driver on
ring 1 use gpu addr 0x0000000080000c04 and cpu addr
0xc00000007c0c8c04</div>
<div>[ 11.021657] radeon 0002:01:00.0: fence driver on
ring 2 use gpu addr 0x0000000080000c08 and cpu addr
0xc00000007c0c8c08</div>
<div>[ 11.031152] radeon 0002:01:00.0: fence driver on
ring 3 use gpu addr 0x0000000080000c0c and cpu addr
0xc00000007c0c8c0c</div>
<div>[ 11.040644] radeon 0002:01:00.0: fence driver on
ring 4 use gpu addr 0x0000000080000c10 and cpu addr
0xc00000007c0c8c10</div>
<div>[ 11.051919] radeon 0002:01:00.0: fence driver on
ring 5 use gpu addr 0x0000000000075a18 and cpu addr
0x8000080088db5a18</div>
</div>
<div><br>
</div>
<div>It's also using bit 63 & 62. So this might be
something to look into.</div>
</span></div>
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<br>
No, that is just the virtual address of the buffer in kernel space
and perfectly ok.<br>
<br>
What you could try is to force the need_dma32 flag to true, see
drivers/gpu/drm/radeon/radeon_<wbr>ttm.c and search for need_dma32.<br>
<br>
Regards,<br>
Christian.<br>
<br>
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<div><br>
</div>
<div>Bas Vermeulen</div>
<div><br>
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