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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Hi Alex,<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:9.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">When set hdp bit, the poll reg mem command will do follow sequence:<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:9.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Write reference value to reg0,<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:9.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Poll reg1,
<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:9.0pt"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Compare
</span><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#00B050">the reference with the reg1 value&mask(The detail behavior information is from sdma team),<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">but in our use case the reference value is not equal to mask, also may not equal to the reg1 value, so the compare won’t pass, so causes the sdma hang.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> Also verified the detail behavior with follow test:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> Use the original method to do invalidate request and poll ack, but replace the mask with ref, then the sdma also will hang:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> uint32_t reg0, uint32_t reg1,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> uint32_t ref, uint32_t mask)<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">{<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"> amdgpu_ring_emit_wreg(ring, reg0, ref);<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:.5in;line-height:150%"><span style="font-size:11.0pt;line-height:150%;font-family:"Calibri",sans-serif;color:#1F497D">//amdgpu_ring_emit_reg_wait(ring, reg1,
</span><span style="font-size:11.0pt;line-height:150%;font-family:"Calibri",sans-serif;color:red">mask</span><span style="font-size:11.0pt;line-height:150%;font-family:"Calibri",sans-serif;color:#1F497D">, mask);<o:p></o:p></span></p>
<p class="MsoNormal" style="line-height:150%"><span style="font-size:11.0pt;line-height:150%;font-family:"Calibri",sans-serif;color:#1F497D"> amdgpu_ring_emit_reg_wait(ring, reg1,
</span><span style="font-size:11.0pt;line-height:150%;font-family:"Calibri",sans-serif;color:red">ref</span><span style="font-size:11.0pt;line-height:150%;font-family:"Calibri",sans-serif;color:#1F497D">, mask);<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">}<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:9.0pt;color:#1F497D">Best Wishes,<o:p></o:p></span></b></p>
<p class="MsoNormal"><b><span style="font-size:9.0pt;color:#1F497D">Emily Deng</span></b><b><i><span style="font-family:\4EFF\5B8B;color:#1F497D"><o:p></o:p></span></i></b></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Deucher, Alexander
<br>
<b>Sent:</b> Friday, March 30, 2018 8:55 PM<br>
<b>To:</b> Deng, Emily <Emily.Deng@amd.com>; amd-gfx@lists.freedesktop.org<br>
<b>Subject:</b> Re: [PATCH] drm/amdgpu/sdma4:fix sdma engine hang<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p><span style="font-family:"Calibri",sans-serif;color:black">The spec claims it does and we use it for HDP flush...<o:p></o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif;color:black">Acked-by: Alex Deucher <<a href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>><o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:black"> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>>
on behalf of Emily Deng <<a href="mailto:Emily.Deng@amd.com">Emily.Deng@amd.com</a>><br>
<b>Sent:</b> Friday, March 30, 2018 4:24:08 AM<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
<b>Cc:</b> Deng, Emily<br>
<b>Subject:</b> [PATCH] drm/amdgpu/sdma4:fix sdma engine hang</span> <o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt">The sdma doesn't support register write and wait in one command.<br>
Use this will make sdma engine hang.<br>
<br>
Signed-off-by: Emily Deng <<a href="mailto:Emily.Deng@amd.com">Emily.Deng@amd.com</a>><br>
---<br>
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 9 +--------<br>
1 file changed, 1 insertion(+), 8 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c<br>
index 9ac28b2..84d148d 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c<br>
@@ -1178,13 +1178,6 @@ static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,<br>
sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);<br>
}<br>
<br>
-static void sdma_v4_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,<br>
- uint32_t reg0, uint32_t reg1,<br>
- uint32_t ref, uint32_t mask)<br>
-{<br>
- sdma_v4_0_wait_reg_mem(ring, 0, 1, reg0, reg1, ref, mask, 10);<br>
-}<br>
-<br>
static int sdma_v4_0_early_init(void *handle)<br>
{<br>
struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
@@ -1626,7 +1619,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {<br>
.pad_ib = sdma_v4_0_ring_pad_ib,<br>
.emit_wreg = sdma_v4_0_ring_emit_wreg,<br>
.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,<br>
- .emit_reg_write_reg_wait = sdma_v4_0_ring_emit_reg_write_reg_wait,<br>
+ .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,<br>
};<br>
<br>
static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)<br>
-- <br>
2.7.4<br>
<br>
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