<div dir="ltr"><div>Can you be more specific, Christian? Mesa has this, I don't think it needs anything else:<br><a href="https://cgit.freedesktop.org/mesa/mesa/commit/?id=7d2079908d9ef05ec3f35b7078833e57846cab5b">https://cgit.freedesktop.org/mesa/mesa/commit/?id=7d2079908d9ef05ec3f35b7078833e57846cab5b</a><br><br></div>Marek<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Mar 28, 2018 at 3:46 AM, Christian König <span dir="ltr"><<a href="mailto:ckoenig.leichtzumerken@gmail.com" target="_blank">ckoenig.leichtzumerken@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">Am 28.03.2018 um 00:22 schrieb Samuel Li:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
It's auto by default. For CZ/ST, auto setting enables sg display<br>
when vram size is small; otherwise still uses vram.<br>
This patch fixed some potential hang issue introduced by change<br>
"allow framebuffer in GART memory as well" due to CZ/ST hardware<br>
limitation.<br>
</blockquote>
<br></span>
Well that is still a NAK.<br>
<br>
As discussed now multiple times please implement the necessary changes in Mesa.<br>
<br>
Regards,<br>
Christian.<div class="HOEnZb"><div class="h5"><br>
<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
v2: Change default setting to auto, also some misc changes.<br>
Signed-off-by: Samuel Li <<a href="mailto:Samuel.Li@amd.com" target="_blank">Samuel.Li@amd.com</a>><br>
---<br>
  drivers/gpu/drm/amd/amdgpu/amd<wbr>gpu.h               |  1 +<br>
  drivers/gpu/drm/amd/amdgpu/amd<wbr>gpu_display.c       | 10 ++++++++--<br>
  drivers/gpu/drm/amd/amdgpu/amd<wbr>gpu_display.h       |  2 ++<br>
  drivers/gpu/drm/amd/amdgpu/amd<wbr>gpu_drv.c           |  4 ++++<br>
  drivers/gpu/drm/amd/amdgpu/amd<wbr>gpu_fb.c            |  2 ++<br>
  drivers/gpu/drm/amd/display/am<wbr>dgpu_dm/amdgpu_dm.c |  3 ++-<br>
  6 files changed, 19 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu.h b/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu.h<br>
index a7e2229..c942362 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu.h<br>
@@ -129,6 +129,7 @@ extern int amdgpu_lbpw;<br>
  extern int amdgpu_compute_multipipe;<br>
  extern int amdgpu_gpu_recovery;<br>
  extern int amdgpu_emu_mode;<br>
+extern int amdgpu_sg_display;<br>
    #ifdef CONFIG_DRM_AMDGPU_SI<br>
  extern int amdgpu_si_support;<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_display.c<br>
index 5495b29..1e7b950 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_display.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_display.c<br>
@@ -513,8 +513,14 @@ uint32_t amdgpu_display_framebuffer_dom<wbr>ains(struct amdgpu_device *adev)<br>
  #if defined(CONFIG_DRM_AMD_DC)<br>
        if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&<br>
            adev->flags & AMD_IS_APU &&<br>
-           amdgpu_device_asic_has_dc_sup<wbr>port(adev->asic_type))<br>
-               domain |= AMDGPU_GEM_DOMAIN_GTT;<br>
+           amdgpu_device_asic_has_dc_sup<wbr>port(adev->asic_type)) {<br>
+               if (amdgpu_sg_display == 1)<br>
+                       domain = AMDGPU_GEM_DOMAIN_GTT;<br>
+               else if (amdgpu_sg_display == -1) {<br>
+                       if (adev->gmc.real_vram_size < AMDGPU_SG_THRESHOLD)<br>
+                               domain = AMDGPU_GEM_DOMAIN_GTT;<br>
+               }<br>
+       }<br>
  #endif<br>
        return domain;<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_display.h<br>
index 2b11d80..2b25393 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_display.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_display.h<br>
@@ -23,6 +23,8 @@<br>
  #ifndef __AMDGPU_DISPLAY_H__<br>
  #define __AMDGPU_DISPLAY_H__<br>
  +#define AMDGPU_SG_THRESHOLD  (256*1024*1024)<br>
+<br>
  uint32_t amdgpu_display_framebuffer_dom<wbr>ains(struct amdgpu_device *adev);<br>
  struct drm_framebuffer *<br>
  amdgpu_display_user_framebuffe<wbr>r_create(struct drm_device *dev,<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_drv.c<br>
index 1bfce79..19f11a5 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_drv.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_drv.c<br>
@@ -132,6 +132,7 @@ int amdgpu_lbpw = -1;<br>
  int amdgpu_compute_multipipe = -1;<br>
  int amdgpu_gpu_recovery = -1; /* auto */<br>
  int amdgpu_emu_mode = 0;<br>
+int amdgpu_sg_display = -1;<br>
    MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");<br>
  module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);<br>
@@ -290,6 +291,9 @@ module_param_named(gpu_recover<wbr>y, amdgpu_gpu_recovery, int, 0444);<br>
  MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");<br>
  module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);<br>
  +MODULE_PARM_DESC(sg_display, "Enable scatter gather display, (1 = enable, 0 = disable, -1 = auto");<br>
+module_param_named(sg_display<wbr>, amdgpu_sg_display, int, 0444);<br>
+<br>
  #ifdef CONFIG_DRM_AMDGPU_SI<br>
    #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODU<wbr>LE)<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_fb.c<br>
index 1206301..f57c355 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_fb.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/a<wbr>mdgpu_fb.c<br>
@@ -138,6 +138,8 @@ static int amdgpufb_create_pinned_object(<wbr>struct amdgpu_fbdev *rfbdev,<br>
        mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,<br>
                                                  fb_tiled);<br>
        domain = amdgpu_display_framebuffer_dom<wbr>ains(adev);<br>
+       if (domain & AMDGPU_GEM_DOMAIN_GTT)<br>
+               DRM_DEBUG_DRIVER("Scatter gather display: enabled\n");<br>
        height = ALIGN(mode_cmd->height, 8);<br>
        size = mode_cmd->pitches[0] * height;<br>
diff --git a/drivers/gpu/drm/amd/display/<wbr>amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/<wbr>amdgpu_dm/amdgpu_dm.c<br>
index 68ab325..7e9f247 100644<br>
--- a/drivers/gpu/drm/amd/display/<wbr>amdgpu_dm/amdgpu_dm.c<br>
+++ b/drivers/gpu/drm/amd/display/<wbr>amdgpu_dm/amdgpu_dm.c<br>
@@ -3074,7 +3074,8 @@ static int dm_plane_helper_prepare_fb(str<wbr>uct drm_plane *plane,<br>
                domain = AMDGPU_GEM_DOMAIN_VRAM;<br>
        r = amdgpu_bo_pin(rbo, domain, &afb->address);<br>
-<br>
+       rbo->preferred_domains = domain;<br>
+       rbo->allowed_domains = domain;<br>
        amdgpu_bo_unreserve(rbo);<br>
        if (unlikely(r != 0)) {<br>
</blockquote>
<br></div></div><div class="HOEnZb"><div class="h5">
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