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<p style="margin-top: 0px; margin-bottom: 0px;">Reviewed-by: Rex Zhu <Rex.Zhu@amd.com></p>
<p style="margin-top: 0px; margin-bottom: 0px;"> </p>
<p style="margin-top: 0px; margin-bottom: 0px;">Best Regards</p>
<p style="margin-top: 0px; margin-bottom: 0px;">Rex<br>
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<div id="divRplyFwdMsg" dir="ltr"><font color="#000000" face="Calibri, sans-serif" style="font-size: 11pt;"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Alex Deucher <alexdeucher@gmail.com><br>
<b>Sent:</b> Thursday, April 12, 2018 6:59 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Deucher, Alexander<br>
<b>Subject:</b> [PATCH] drm/amdgpu/powerplay: fix smu7_get_memory_type for fiji</font>
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<div class="PlainText">Fiji uses a different register than other smu7 asics, but<br>
we already have this info in the base driver so just<br>
use that.<br>
<br>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com><br>
---<br>
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 8 ++------<br>
1 file changed, 2 insertions(+), 6 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
index 21c021ba0f49..97b7c2333f19 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
@@ -4150,13 +4150,9 @@ static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)<br>
static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)<br>
{<br>
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);<br>
- uint32_t temp;<br>
-<br>
- temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);<br>
+ struct amdgpu_device *adev = hwmgr->adev;<br>
<br>
- data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==<br>
- ((temp & MC_SEQ_MISC0_GDDR5_MASK) >><br>
- MC_SEQ_MISC0_GDDR5_SHIFT));<br>
+ data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5);<br>
<br>
return 0;<br>
}<br>
-- <br>
2.13.6<br>
<br>
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