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<p style="margin-top:0;margin-bottom:0">Does this actually work on SR-IOV? Or does it just seem to but nothing bad happens because we get a GPU reset on a world switch? The behavior of this packet should be the same as SDMA and that definitely doesn't work.
I don't see why this would be any different.</p>
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<p style="margin-top:0;margin-bottom:0">Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
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<p style="margin-top:0;margin-bottom:0">Alex<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Christian König <ckoenig.leichtzumerken@gmail.com><br>
<b>Sent:</b> Tuesday, April 17, 2018 9:01:35 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Subject:</b> [PATCH] drm/amdgpu: limit reg_write_reg_wait workaround to SRIOV</font>
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<div class="PlainText">Turned out that this locks up some bare metal Vega10.<br>
<br>
Signed-off-by: Christian König <christian.koenig@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 ++++++-<br>
1 file changed, 6 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
index 583f6f616dd3..5329d7e5fb71 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
@@ -4144,7 +4144,12 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,<br>
{<br>
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);<br>
<br>
- gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, ref, mask, 0x20);<br>
+ if (amdgpu_sriov_vf(adev))<br>
+ gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,<br>
+ ref, mask, 0x20);<br>
+ else<br>
+ amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,<br>
+ ref, mask);<br>
}<br>
<br>
static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,<br>
-- <br>
2.14.1<br>
<br>
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