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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Hi all,<o:p></o:p></span></p>
<p class="MsoNormal">Does this actually work on SR-IOV? Or does it just seem to but nothing bad happens because we get a GPU reset on a world switch?<o:p></o:p></p>
<p class="MsoNormal">I honestly don't know. I think that SR-IOV uses a specialized firmware where this packet has a different meaning.<br>
<br>
But the real fix would be to get the RLC firmware fix to not reinitialize those regs to zero on world switch.<br>
<span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">[Emily]Yes, it actually works on SR-IOV, it fixes lots of engine hang issue.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:9.0pt;color:#1F497D">Best Wishes,<o:p></o:p></span></b></p>
<p class="MsoNormal"><b><span style="font-size:9.0pt;color:#1F497D">Emily Deng</span></b><b><i><span style="font-family:\4EFF\5B8B;color:#1F497D"><o:p></o:p></span></i></b></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:windowtext">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:windowtext"> Christian König [mailto:ckoenig.leichtzumerken@gmail.com]
<br>
<b>Sent:</b> Tuesday, April 17, 2018 11:27 PM<br>
<b>To:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com><br>
<b>Subject:</b> Re: [PATCH] drm/amdgpu: limit reg_write_reg_wait workaround to SRIOV<o:p></o:p></span></p>
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<p class="MsoNormal">Does this actually work on SR-IOV? Or does it just seem to but nothing bad happens because we get a GPU reset on a world switch?<o:p></o:p></p>
</blockquote>
<p class="MsoNormal">I honestly don't know. I think that SR-IOV uses a specialized firmware where this packet has a different meaning.<br>
<br>
But the real fix would be to get the RLC firmware fix to not reinitialize those regs to zero on world switch.<br>
<br>
Christian.<br>
<br>
Am 17.04.2018 um 16:02 schrieb Deucher, Alexander:<o:p></o:p></p>
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<p><span style="font-family:"Calibri",sans-serif">Does this actually work on SR-IOV? Or does it just seem to but nothing bad happens because we get a GPU reset on a world switch? The behavior of this packet should be the same as SDMA and that definitely doesn't
work. I don't see why this would be any different.<o:p></o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif"><o:p> </o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif">Acked-by: Alex Deucher <a href="mailto:alexander.deucher@amd.com">
<alexander.deucher@amd.com></a><o:p></o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif"><o:p> </o:p></span></p>
<p><span style="font-family:"Calibri",sans-serif">Alex<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> amd-gfx
<a href="mailto:amd-gfx-bounces@lists.freedesktop.org"><amd-gfx-bounces@lists.freedesktop.org></a> on behalf of Christian König
<a href="mailto:ckoenig.leichtzumerken@gmail.com"><ckoenig.leichtzumerken@gmail.com></a><br>
<b>Sent:</b> Tuesday, April 17, 2018 9:01:35 AM<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
<b>Subject:</b> [PATCH] drm/amdgpu: limit reg_write_reg_wait workaround to SRIOV</span>
<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt">Turned out that this locks up some bare metal Vega10.<br>
<br>
Signed-off-by: Christian König <a href="mailto:christian.koenig@amd.com"><christian.koenig@amd.com></a><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 ++++++-<br>
1 file changed, 6 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
index 583f6f616dd3..5329d7e5fb71 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
@@ -4144,7 +4144,12 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,<br>
{<br>
int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);<br>
<br>
- gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, ref, mask, 0x20);<br>
+ if (amdgpu_sriov_vf(adev))<br>
+ gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,<br>
+ ref, mask, 0x20);<br>
+ else<br>
+ amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,<br>
+ ref, mask);<br>
}<br>
<br>
static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,<br>
-- <br>
2.14.1<br>
<br>
_______________________________________________<br>
amd-gfx mailing list<br>
<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
<a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><o:p></o:p></span></p>
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