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<p style="margin-top:0;margin-bottom:0">Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of mikita.lipski@amd.com <mikita.lipski@amd.com><br>
<b>Sent:</b> Tuesday, May 29, 2018 5:51 PM<br>
<b>To:</b> Zhu, Rex; Deucher, Alexander; amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Lipski, Mikita; Wu, Hersen; Wentland, Harry<br>
<b>Subject:</b> [PATCH] drm/amd/pp: Connect display_clock_voltage_request to a function pointer</font>
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<div class="PlainText">From: Mikita Lipski <mikita.lipski@amd.com><br>
<br>
Get rid of an empty dublicate of smu10_display_clock_voltage_request<br>
<br>
Add display_clock_voltage_request to smu10 functions struct so it<br>
can be called from outside the class and connect the pointer to<br>
the function.<br>
<br>
That way Display driver can finally apply clock voltage requests<br>
when needed.<br>
<br>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com><br>
---<br>
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 63 +++++++++++------------<br>
 1 file changed, 30 insertions(+), 33 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c<br>
index e160b05..74136ed 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c<br>
@@ -53,8 +53,36 @@ static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;<br>
 <br>
 <br>
 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,<br>
-               struct pp_display_clock_request *clock_req);<br>
+               struct pp_display_clock_request *clock_req)<br>
+{<br>
+       struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);<br>
+       enum amd_pp_clock_type clk_type = clock_req->clock_type;<br>
+       uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;<br>
+       PPSMC_Msg        msg;<br>
+<br>
+       switch (clk_type) {<br>
+       case amd_pp_dcf_clock:<br>
+               if (clk_freq == smu10_data->dcf_actual_hard_min_freq)<br>
+                       return 0;<br>
+               msg =  PPSMC_MSG_SetHardMinDcefclkByFreq;<br>
+               smu10_data->dcf_actual_hard_min_freq = clk_freq;<br>
+               break;<br>
+       case amd_pp_soc_clock:<br>
+                msg = PPSMC_MSG_SetHardMinSocclkByFreq;<br>
+               break;<br>
+       case amd_pp_f_clock:<br>
+               if (clk_freq == smu10_data->f_actual_hard_min_freq)<br>
+                       return 0;<br>
+               smu10_data->f_actual_hard_min_freq = clk_freq;<br>
+               msg = PPSMC_MSG_SetHardMinFclkByFreq;<br>
+               break;<br>
+       default:<br>
+               return -EINVAL;<br>
+       }<br>
+       smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq);<br>
 <br>
+       return 0;<br>
+}<br>
 <br>
 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)<br>
 {<br>
@@ -1023,39 +1051,7 @@ static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,<br>
         return 0;<br>
 }<br>
 <br>
-static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,<br>
-               struct pp_display_clock_request *clock_req)<br>
-{<br>
-       struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);<br>
-       enum amd_pp_clock_type clk_type = clock_req->clock_type;<br>
-       uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;<br>
-       PPSMC_Msg        msg;<br>
-<br>
-       switch (clk_type) {<br>
-       case amd_pp_dcf_clock:<br>
-               if (clk_freq == smu10_data->dcf_actual_hard_min_freq)<br>
-                       return 0;<br>
-               msg =  PPSMC_MSG_SetHardMinDcefclkByFreq;<br>
-               smu10_data->dcf_actual_hard_min_freq = clk_freq;<br>
-               break;<br>
-       case amd_pp_soc_clock:<br>
-                msg = PPSMC_MSG_SetHardMinSocclkByFreq;<br>
-               break;<br>
-       case amd_pp_f_clock:<br>
-               if (clk_freq == smu10_data->f_actual_hard_min_freq)<br>
-                       return 0;<br>
-               smu10_data->f_actual_hard_min_freq = clk_freq;<br>
-               msg = PPSMC_MSG_SetHardMinFclkByFreq;<br>
-               break;<br>
-       default:<br>
-               pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");<br>
-               return -EINVAL;<br>
-       }<br>
-<br>
-       smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq);<br>
 <br>
-       return 0;<br>
-}<br>
 <br>
 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)<br>
 {<br>
@@ -1188,6 +1184,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {<br>
         .set_mmhub_powergating_by_smu = smu10_set_mmhub_powergating_by_smu,<br>
         .smus_notify_pwe = smu10_smus_notify_pwe,<br>
         .gfx_off_control = smu10_gfx_off_control,<br>
+       .display_clock_voltage_request = smu10_display_clock_voltage_request,<br>
 };<br>
 <br>
 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)<br>
-- <br>
2.7.4<br>
<br>
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