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<p style="margin-top:0;margin-bottom:0"><span>Reviewed-by: <span>Rex Zhu <Rex.Zhu@amd.com></span><br>
</span></p>
<p style="margin-top:0;margin-bottom:0"><span><br>
</span></p>
<p style="margin-top:0;margin-bottom:0"><span>Best Regards</span></p>
<p style="margin-top:0;margin-bottom:0"><span>Rex</span><br>
</p>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" color="#000000" face="Calibri, sans-serif"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Evan Quan <evan.quan@amd.com><br>
<b>Sent:</b> Wednesday, June 6, 2018 1:54 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Quan, Evan; Zhu, Rex<br>
<b>Subject:</b> [PATCH] drm/amd/powerplay: fix wrong clock adjust sequence</font>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">The clocks should be adjusted after display configuration changed.<br>
Otherwise, the socclk and memclk may be forced on an unnecessary higher<br>
level.<br>
<br>
Change-Id: I0170e968ba1f64d15d4238b658eefc307adc2642<br>
Signed-off-by: Evan Quan <evan.quan@amd.com><br>
---<br>
drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 13 ++++++-------<br>
1 file changed, 6 insertions(+), 7 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c<br>
index 0af13c1..323990b 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c<br>
@@ -265,19 +265,18 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,<br>
if (skip)<br>
return 0;<br>
<br>
- if (!hwmgr->ps)<br>
- /*<br>
- * for vega12/vega20 which does not support power state manager<br>
- * DAL clock limits should also be honoured<br>
- */<br>
- phm_apply_clock_adjust_rules(hwmgr);<br>
-<br>
phm_pre_display_configuration_changed(hwmgr);<br>
<br>
phm_display_configuration_changed(hwmgr);<br>
<br>
if (hwmgr->ps)<br>
power_state_management(hwmgr, new_ps);<br>
+ else<br>
+ /*<br>
+ * for vega12/vega20 which does not support power state manager<br>
+ * DAL clock limits should also be honoured<br>
+ */<br>
+ phm_apply_clock_adjust_rules(hwmgr);<br>
<br>
phm_notify_smc_display_config_after_ps_adjustment(hwmgr);<br>
<br>
-- <br>
2.7.4<br>
<br>
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