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<p style="margin-top:0;margin-bottom:0"><span>Acked-by: Rex Zhu<rezhu@amd.com></span></p>
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Best Regards</div>
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Rex<br>
<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Kenneth Feng <kenneth.feng@amd.com><br>
<b>Sent:</b> Tuesday, June 12, 2018 10:54 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Feng, Kenneth<br>
<b>Subject:</b> [PATCH] drm/amd/powerplay: Set higher SCLK&MCLK frequency than dpm7 in OD</font>
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<div class="BodyFragment" data-find="_4"><font size="2" data-find="_3"><span style="font-size:11pt;" data-find="_2">
<div class="PlainText" data-find="_1">Fix the issue that SCLK&MCLK can't be set higher than dpm7 when<br>
OD is enabled in SMU7.<br>
<br>
Change-Id: If8249795739e29a063154cffce693b3c77cca151<br>
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com><br>
---<br>
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 5 ++++-<br>
1 file changed, 4 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
index b763c54..11e1762 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
@@ -3762,7 +3762,10 @@ static int smu7_generate_dpm_level_enable_mask(<br>
const struct smu7_power_state *smu7_ps =<br>
cast_const_phw_smu7_power_state(states->pnew_state);<br>
<br>
- result = smu7_trim_dpm_states(hwmgr, smu7_ps);<br>
+ /*skip the trim if od is enabled*/<br>
+ if (!hwmgr->od_enabled)<br>
+ result = smu7_trim_dpm_states(hwmgr, smu7_ps);<br>
+<br>
if (result)<br>
return result;<br>
<br>
-- <br>
2.7.4<br>
<br>
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