<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> <style type="text/css" style="display:none;"></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size: 12pt; color: rgb(0, 0, 0); font-family: Calibri, Helvetica, sans-serif, "EmojiFont", "Apple Color Emoji", "Segoe UI Emoji", NotoColorEmoji, "Segoe UI Symbol", "Android Emoji", EmojiSymbols;" dir="ltr"> <p style="margin-top:0;margin-bottom:0">Acked-by: Alex Deucher <alexander.deucher@amd.com><br> </p> <br> <div style="color: rgb(0, 0, 0);"> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Shaoyun Liu <Shaoyun.Liu@amd.com><br> <b>Sent:</b> Tuesday, June 12, 2018 1:38 PM<br> <b>To:</b> amd-gfx@lists.freedesktop.org<br> <b>Cc:</b> Liu, Shaoyun<br> <b>Subject:</b> [PATCH] drm/amd/include: Update df 3.6 mask and shift definition</font> <div> </div> </div> <div class="BodyFragment"><font size="2"><span style="font-size:11pt;"> <div class="PlainText">The register field hsas been changed in df 3.6, update to correct setting<br> <br> Change-Id: Id625d7698b610c07081f421537964686f8f0b67c<br> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com><br> ---<br> drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h | 8 ++++----<br> 1 file changed, 4 insertions(+), 4 deletions(-)<br> <br> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h<br> index 88f7c69..06fac50 100644<br> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h<br> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h<br> @@ -36,13 +36,13 @@<br> /* DF_CS_AON0_DramBaseAddress0 */<br> #define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0<br> #define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1<br> -#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4<br> -#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8<br> +#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x2<br> +#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x9<br> #define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc<br> #define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L<br> #define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L<br> -#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L<br> -#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L<br> +#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x0000003CL<br> +#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000E00L<br> #define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L<br> <br> #endif<br> -- <br> 1.9.1<br> <br> _______________________________________________<br> amd-gfx mailing list<br> amd-gfx@lists.freedesktop.org<br> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx" id="LPlnk712828" class="OWAAutoLink" previewremoved="true">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br> </div> </span></font></div> </div> </div> </body> </html>