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<br>
Move this change to  patch3.
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Rex Zhu <Rex.Zhu@amd.com><br>
<b>Sent:</b> Wednesday, June 13, 2018 7:18 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Zhu, Rex<br>
<b>Subject:</b> [PATCH 4/7] drm/amd/pp: Add gfx pg support in smu through set_powergating_by_smu</font>
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<div class="PlainText" data-find="_1">gfx ip block can call set_powergating_by_smu to set gfx pg state if<br>
necessary.<br>
<br>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         | 10 ++++------<br>
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       |  4 ++--<br>
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 16 ++++++++++++++++<br>
 3 files changed, 22 insertions(+), 8 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
index 807ee0d..916776a 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
@@ -5591,14 +5591,12 @@ static int gfx_v8_0_late_init(void *handle)<br>
 static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,<br>
                                                        bool enable)<br>
 {<br>
-       if ((adev->asic_type == CHIP_POLARIS11) ||<br>
+       if (((adev->asic_type == CHIP_POLARIS11) ||<br>
             (adev->asic_type == CHIP_POLARIS12) ||<br>
-           (adev->asic_type == CHIP_VEGAM))<br>
+           (adev->asic_type == CHIP_VEGAM)) &&<br>
+           adev->powerplay.pp_funcs->set_powergating_by_smu)<br>
                 /* Send msg to SMU via Powerplay */<br>
-               amdgpu_device_ip_set_powergating_state(adev,<br>
-                                                      AMD_IP_BLOCK_TYPE_SMC,<br>
-                                                      enable ?<br>
-                                                      AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);<br>
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);<br>
 <br>
         WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);<br>
 }<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c<br>
index 377f536..85cf2f9 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c<br>
@@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,<br>
                                                 RENG_EXECUTE_ON_REG_UPDATE, 1);<br>
                 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);<br>
 <br>
-               if (adev->powerplay.pp_funcs->powergate_mmhub)<br>
-                       amdgpu_dpm_powergate_mmhub(adev);<br>
+               if (adev->powerplay.pp_funcs->set_powergating_by_smu)<br>
+                       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, 0);<br>
 <br>
         } else {<br>
                 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,<br>
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c<br>
index f68551f..cb2dd7c 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c<br>
@@ -1184,6 +1184,21 @@ static int pp_dpm_powergate_mmhub(void *handle)<br>
         return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);<br>
 }<br>
 <br>
+static int pp_dpm_powergate_gfx(void *handle, bool gate)<br>
+{<br>
+       struct pp_hwmgr *hwmgr = handle;<br>
+<br>
+       if (!hwmgr || !hwmgr->pm_en)<br>
+               return 0;<br>
+<br>
+       if (hwmgr->hwmgr_func->powergate_gfx == NULL) {<br>
+               pr_info("%s was not implemented.\n", __func__);<br>
+               return 0;<br>
+       }<br>
+<br>
+       return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate);<br>
+}<br>
+<br>
 static int pp_set_powergating_by_smu(void *handle,<br>
                                 uint32_t block_type, bool gate)<br>
 {<br>
@@ -1201,6 +1216,7 @@ static int pp_set_powergating_by_smu(void *handle,<br>
                 pp_dpm_powergate_mmhub(handle);<br>
                 break;<br>
         case AMD_IP_BLOCK_TYPE_GFX:<br>
+               ret = pp_dpm_powergate_gfx(handle, gate);<br>
                 break;<br>
         default:<br>
                 break;<br>
-- <br>
1.9.1<br>
<br>
_______________________________________________<br>
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