<div dir="auto">Acked-by: Marek Olšák <<a href="mailto:marek.olsak@amd.com">marek.olsak@amd.com</a>><div dir="auto"><br></div><div dir="auto">Marek</div></div><br><div class="gmail_quote"><div dir="ltr">On Fri, Jun 15, 2018, 4:03 AM zhoucm1 <<a href="mailto:zhoucm1@amd.com">zhoucm1@amd.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Marek, Can I get your RB or Acked on this patches? Since these info are <br>
reported to UMD.<br>
<br>
<br>
Thanks,<br>
<br>
David Zhou<br>
<br>
<br>
On 2018年06月15日 15:22, zhoucm1 wrote:<br>
><br>
><br>
> On 2018年06月15日 15:16, Zhang, Jerry wrote:<br>
>>> -----Original Message-----<br>
>>> From: amd-gfx [mailto:<a href="mailto:amd-gfx-bounces@lists.freedesktop.org" target="_blank" rel="noreferrer">amd-gfx-bounces@lists.freedesktop.org</a>] On <br>
>>> Behalf Of<br>
>>> Christian K?nig<br>
>>> Sent: Friday, June 15, 2018 15:09<br>
>>> To: Zhou, David(ChunMing) <<a href="mailto:David1.Zhou@amd.com" target="_blank" rel="noreferrer">David1.Zhou@amd.com</a>>; amd-<br>
>>> <a href="mailto:gfx@lists.freedesktop.org" target="_blank" rel="noreferrer">gfx@lists.freedesktop.org</a><br>
>>> Cc: Olsak, Marek <<a href="mailto:Marek.Olsak@amd.com" target="_blank" rel="noreferrer">Marek.Olsak@amd.com</a>>; Ryan, Sean <<a href="mailto:Sean.Ryan@amd.com" target="_blank" rel="noreferrer">Sean.Ryan@amd.com</a>><br>
>>> Subject: Re: [PATCH] drm/amdgpu: update ib_start/size_alignment same as<br>
>>> windows used<br>
>>><br>
>>> Am 15.06.2018 um 08:45 schrieb Chunming Zhou:<br>
>>>> PAGE_SIZE for start_alignment is far much than hw requirement, And<br>
>>>> now, update to expereince value from window side.<br>
>>>><br>
>>>> Change-Id: I08a7e72076386c32faf36ec4812b30e68dde23e5<br>
>>>> Signed-off-by: Chunming Zhou <<a href="mailto:david1.zhou@amd.com" target="_blank" rel="noreferrer">david1.zhou@amd.com</a>><br>
>>> Acked-by: Christian König <<a href="mailto:christian.koenig@amd.com" target="_blank" rel="noreferrer">christian.koenig@amd.com</a>><br>
>> Acked-by: Junwei Zhang <<a href="mailto:Jerry.Zhang@amd.com" target="_blank" rel="noreferrer">Jerry.Zhang@amd.com</a>><br>
>><br>
>> BTW, any issue it fixes?<br>
> Yes, as talked in internal brahma list " whether ib_start_alignment is <br>
> proper", which fixes some PAL assert checking.<br>
><br>
> Regards,<br>
> David Zhou<br>
>><br>
>> Jerry<br>
>><br>
>>>> ---<br>
>>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 28 <br>
>>>> ++++++++++++++---------<br>
>>> -----<br>
>>>>    1 file changed, 14 insertions(+), 14 deletions(-)<br>
>>>><br>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
>>>> index 392dd24e83f5..d041dddaad0c 100644<br>
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
>>>> @@ -329,35 +329,35 @@ static int amdgpu_info_ioctl(struct <br>
>>>> drm_device *dev,<br>
>>> void *data, struct drm_file<br>
>>>>                type = AMD_IP_BLOCK_TYPE_GFX;<br>
>>>>                for (i = 0; i < adev->gfx.num_gfx_rings; i++)<br>
>>>>                    ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0)<br>
>>> << i);<br>
>>>> -            ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;<br>
>>>> -            ib_size_alignment = 8;<br>
>>>> +            ib_start_alignment = 32;<br>
>>>> +            ib_size_alignment = 32;<br>
>>>>                break;<br>
>>>>            case AMDGPU_HW_IP_COMPUTE:<br>
>>>>                type = AMD_IP_BLOCK_TYPE_GFX;<br>
>>>>                for (i = 0; i < adev->gfx.num_compute_rings; i++)<br>
>>>>                    ring_mask |= ((adev->gfx.compute_ring[i].ready ?<br>
>>> 1 : 0) << i);<br>
>>>> -            ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;<br>
>>>> -            ib_size_alignment = 8;<br>
>>>> +            ib_start_alignment = 32;<br>
>>>> +            ib_size_alignment = 32;<br>
>>>>                break;<br>
>>>>            case AMDGPU_HW_IP_DMA:<br>
>>>>                type = AMD_IP_BLOCK_TYPE_SDMA;<br>
>>>>                for (i = 0; i < adev->sdma.num_instances; i++)<br>
>>>>                    ring_mask |= ((adev-<br>
>>>> sdma.instance[i].ring.ready ? 1 : 0) << i);<br>
>>>> -            ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;<br>
>>>> -            ib_size_alignment = 1;<br>
>>>> +            ib_start_alignment = 256;<br>
>>>> +            ib_size_alignment = 4;<br>
>>>>                break;<br>
>>>>            case AMDGPU_HW_IP_UVD:<br>
>>>>                type = AMD_IP_BLOCK_TYPE_UVD;<br>
>>>>                for (i = 0; i < adev->uvd.num_uvd_inst; i++)<br>
>>>>                    ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 <br>
>>>> : 0)<br>
>>> << i);<br>
>>>> -            ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;<br>
>>>> -            ib_size_alignment = 16;<br>
>>>> +            ib_start_alignment = 64;<br>
>>>> +            ib_size_alignment = 64;<br>
>>>>                break;<br>
>>>>            case AMDGPU_HW_IP_VCE:<br>
>>>>                type = AMD_IP_BLOCK_TYPE_VCE;<br>
>>>>                for (i = 0; i < adev->vce.num_rings; i++)<br>
>>>>                    ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) <<<br>
>>> i);<br>
>>>> -            ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;<br>
>>>> +            ib_start_alignment = 4;<br>
>>>>                ib_size_alignment = 1;<br>
>>>>                break;<br>
>>>>            case AMDGPU_HW_IP_UVD_ENC:<br>
>>>> @@ -367,26 +367,26 @@ static int amdgpu_info_ioctl(struct <br>
>>>> drm_device *dev,<br>
>>> void *data, struct drm_file<br>
>>>>                        ring_mask |=<br>
>>>> ((adev->uvd.inst[i].ring_enc[j].ready ? 1 :<br>
>>> 0) <<<br>
>>>>                        (j + i * adev->uvd.num_enc_rings));<br>
>>>> -            ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;<br>
>>>> -            ib_size_alignment = 1;<br>
>>>> +            ib_start_alignment = 64;<br>
>>>> +            ib_size_alignment = 64;<br>
>>>>                break;<br>
>>>>            case AMDGPU_HW_IP_VCN_DEC:<br>
>>>>                type = AMD_IP_BLOCK_TYPE_VCN;<br>
>>>>                ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;<br>
>>>> -            ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;<br>
>>>> +            ib_start_alignment = 16;<br>
>>>>                ib_size_alignment = 16;<br>
>>>>                break;<br>
>>>>            case AMDGPU_HW_IP_VCN_ENC:<br>
>>>>                type = AMD_IP_BLOCK_TYPE_VCN;<br>
>>>>                for (i = 0; i < adev->vcn.num_enc_rings; i++)<br>
>>>>                    ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0)<br>
>>> << i);<br>
>>>> -            ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;<br>
>>>> +            ib_start_alignment = 64;<br>
>>>>                ib_size_alignment = 1;<br>
>>>>                break;<br>
>>>>            case AMDGPU_HW_IP_VCN_JPEG:<br>
>>>>                type = AMD_IP_BLOCK_TYPE_VCN;<br>
>>>>                ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0;<br>
>>>> -            ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;<br>
>>>> +            ib_start_alignment = 16;<br>
>>>>                ib_size_alignment = 16;<br>
>>>>                break;<br>
>>>>            default:<br>
>>> _______________________________________________<br>
>>> amd-gfx mailing list<br>
>>> <a href="mailto:amd-gfx@lists.freedesktop.org" target="_blank" rel="noreferrer">amd-gfx@lists.freedesktop.org</a><br>
>>> <a href="https://lists.freedesktop.org/mailman/listinfo/amd-gfx" rel="noreferrer noreferrer" target="_blank">https://lists.freedesktop.org/mailman/listinfo/amd-gfx</a><br>
><br>
> _______________________________________________<br>
> amd-gfx mailing list<br>
> <a href="mailto:amd-gfx@lists.freedesktop.org" target="_blank" rel="noreferrer">amd-gfx@lists.freedesktop.org</a><br>
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<br>
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</blockquote></div>