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<p style="margin-top:0;margin-bottom:0">Do we need to maintain the uvd/vce pg state in pp?</p>
<p style="margin-top:0;margin-bottom:0">uvd/vce have maintained the pg state by themselves.</p>
<p style="margin-top:0;margin-bottom:0">pp only provide an interface for uvd/vce/gfx/mmhub to power up/down the ip through smu if smu supported, concurrently enable/disable uvd/vce/mmhub dpm feature.</p>
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<p style="margin-top:0;margin-bottom:0">Best Regards</p>
<p style="margin-top:0;margin-bottom:0">Rex </p>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Alex Deucher <alexdeucher@gmail.com><br>
<b>Sent:</b> Thursday, June 28, 2018 11:31 PM<br>
<b>To:</b> Quan, Evan<br>
<b>Cc:</b> amd-gfx list<br>
<b>Subject:</b> Re: [PATCH] drm/amd/powerplay: initialize uvd/vce powergate status v3</font>
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<div class="PlainText">On Wed, Jun 20, 2018 at 2:40 AM, Evan Quan <evan.quan@amd.com> wrote:<br>
> On UVD/VCE dpm enabled/disabled, the powergate status will be<br>
> set as false/true. So that we will not try to ungate/gate them(<br>
> enable/disable their dpm) again.<br>
><br>
> v2: added check for uvd/vce powergate status before gating<br>
> v3: fix typo in description<br>
><br>
> Change-Id: I569a5aa216b5e7d64a2b504f2ff98cc83ca802d5<br>
> Signed-off-by: Evan Quan <evan.quan@amd.com><br>
<br>
<br>
Does vega10 need a similar fix?<br>
<br>
Alex<br>
<br>
> ---<br>
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 23 ++++++++++++++++++++++<br>
>  1 file changed, 23 insertions(+)<br>
><br>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c<br>
> index 45c8f2d..28b172e 100644<br>
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c<br>
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c<br>
> @@ -777,6 +777,21 @@ static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)<br>
>         return 0;<br>
>  }<br>
><br>
> +static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)<br>
> +{<br>
> +       struct vega12_hwmgr *data =<br>
> +                       (struct vega12_hwmgr *)(hwmgr->backend);<br>
> +<br>
> +       data->uvd_power_gated = true;<br>
> +       data->vce_power_gated = true;<br>
> +<br>
> +       if (data->smu_features[GNLD_DPM_UVD].enabled)<br>
> +               data->uvd_power_gated = false;<br>
> +<br>
> +       if (data->smu_features[GNLD_DPM_VCE].enabled)<br>
> +               data->vce_power_gated = false;<br>
> +}<br>
> +<br>
>  static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)<br>
>  {<br>
>         struct vega12_hwmgr *data =<br>
> @@ -801,6 +816,8 @@ static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)<br>
>                 }<br>
>         }<br>
><br>
> +       vega12_init_powergate_state(hwmgr);<br>
> +<br>
>         return 0;<br>
>  }<br>
><br>
> @@ -1985,6 +2002,9 @@ static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)<br>
>  {<br>
>         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);<br>
><br>
> +       if (data->vce_power_gated == bgate)<br>
> +               return 0;<br>
> +<br>
>         data->vce_power_gated = bgate;<br>
>         vega12_enable_disable_vce_dpm(hwmgr, !bgate);<br>
>  }<br>
> @@ -1993,6 +2013,9 @@ static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)<br>
>  {<br>
>         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);<br>
><br>
> +       if (data->uvd_power_gated == bgate)<br>
> +               return 0;<br>
> +<br>
>         data->uvd_power_gated = bgate;<br>
>         vega12_enable_disable_uvd_dpm(hwmgr, !bgate);<br>
>  }<br>
> --<br>
> 2.7.4<br>
><br>
> _______________________________________________<br>
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> amd-gfx@lists.freedesktop.org<br>
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