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Reviewed-by: Rex Zhu <Rex.Zhu@amd.com></p>
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Best Regards</p>
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Rex</p>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Alex Deucher <alexdeucher@gmail.com><br>
<b>Sent:</b> Friday, June 29, 2018 2:38 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Deucher, Alexander<br>
<b>Subject:</b> [PATCH] drm/amdgpu/pp: fix copy paste typo in smu7_get_pp_table_entry_callback_func_v1</font>
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<div class="PlainText">Should be using PCIELaneLow for the low clock level.<br>
<br>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com><br>
---<br>
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 +-<br>
1 file changed, 1 insertion(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
index e5c27d12aa49..077b79938528 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c<br>
@@ -3183,7 +3183,7 @@ static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,<br>
performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,<br>
state_entry->ucPCIEGenLow);<br>
performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,<br>
- state_entry->ucPCIELaneHigh);<br>
+ state_entry->ucPCIELaneLow);<br>
<br>
performance_level = &(smu7_power_state->performance_levels<br>
[smu7_power_state->performance_level_count++]);<br>
-- <br>
2.13.6<br>
<br>
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