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<p style="margin-top:0;margin-bottom:0"><span>Reviewed-by: Evan Quan <evan.quan@amd.com></span><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Rex Zhu <rex.zhu@amd.com><br>
<b>Sent:</b> Thursday, July 5, 2018 4:39:44 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Zhu, Rex<br>
<b>Subject:</b> [PATCH] drm/amdgpu: Add CLK IP base offset</font>
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<div class="PlainText">so we can read/write the registers in CLK domain<br>
through RREG32/WREG32_SOC15<br>
<br>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +<br>
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 1 +<br>
2 files changed, 2 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
index 44bcc3e..8eaba0f 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
@@ -1401,6 +1401,7 @@ enum amd_hw_ip_block_type {<br>
PWR_HWIP,<br>
NBIF_HWIP,<br>
THM_HWIP,<br>
+ CLK_HWIP,<br>
MAX_HWIP<br>
};<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c<br>
index 45aafca..c5c9b2b 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c<br>
@@ -51,6 +51,7 @@ int vega10_reg_base_init(struct amdgpu_device *adev)<br>
adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i]));<br>
adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i]));<br>
adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));<br>
+ adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));<br>
}<br>
return 0;<br>
}<br>
-- <br>
1.9.1<br>
<br>
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