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<div class="moz-cite-prefix">Looks like the patches should be
reordered, e.g. patch #2 should be the last.<br>
<br>
Apart from that Reviewed-by: Christian König
<a class="moz-txt-link-rfc2396E" href="mailto:christian.koenig@amd.com"><christian.koenig@amd.com></a>.<br>
<br>
Regards,<br>
Christian.<br>
<br>
Am 09.07.2018 um 18:54 schrieb Deucher, Alexander:<br>
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<p style="margin-top:0;margin-bottom:0">Series is:</p>
<p style="margin-top:0;margin-bottom:0">Reviewed-by: Alex
Deucher <a class="moz-txt-link-rfc2396E" href="mailto:alexander.deucher@amd.com"><alexander.deucher@amd.com></a><br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt"
color="#000000" face="Calibri, sans-serif"><b>From:</b>
amd-gfx <a class="moz-txt-link-rfc2396E" href="mailto:amd-gfx-bounces@lists.freedesktop.org"><amd-gfx-bounces@lists.freedesktop.org></a> on
behalf of Leo Liu <a class="moz-txt-link-rfc2396E" href="mailto:leo.liu@amd.com"><leo.liu@amd.com></a><br>
<b>Sent:</b> Monday, July 9, 2018 12:11:38 PM<br>
<b>To:</b> <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
<b>Cc:</b> Liu, Leo<br>
<b>Subject:</b> [PATCH 3/3] drm/amdgpu: move cache window
setup after power and clock resume</font>
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<div class="PlainText">To make register read/write reliable.
Along with the previous patch,<br>
VCN will work with dpm disabled case.<br>
<br>
Signed-off-by: Leo Liu <a class="moz-txt-link-rfc2396E" href="mailto:leo.liu@amd.com"><leo.liu@amd.com></a><br>
---<br>
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++--<br>
1 file changed, 2 insertions(+), 2 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c<br>
index b82c92084b6f..ca4265bc10b9 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c<br>
@@ -600,12 +600,12 @@ static int vcn_v1_0_start(struct
amdgpu_device *adev)<br>
/* disable byte swapping */<br>
lmi_swap_cntl = 0;<br>
<br>
- vcn_v1_0_mc_resume(adev);<br>
-<br>
vcn_1_0_disable_static_power_gating(adev);<br>
/* disable clock gating */<br>
vcn_v1_0_disable_clock_gating(adev);<br>
<br>
+ vcn_v1_0_mc_resume(adev);<br>
+<br>
/* disable interupt */<br>
WREG32_P(SOC15_REG_OFFSET(UVD, 0,
mmUVD_MASTINT_EN), 0,<br>
~UVD_MASTINT_EN__VCPU_EN_MASK);<br>
-- <br>
2.17.1<br>
<br>
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