<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <style type="text/css" style="display:none;"></style> </head> <body dir="ltr"> <div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr"> Yes, agree! It's better to use that existing function. Will change it accordingly. Thanks, Boyuan </div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr">From: Liu, Leo Sent: July 19, 2018 2:13:50 PM To: Zhang, Boyuan; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 3/5] drm/amdgpu: enable system interrupt for jrbc <div> </div> </div> <div class="BodyFragment"> <div class="PlainText"> On 07/18/2018 04:39 PM, boyuan.zhang@amd.com wrote: > From: Boyuan Zhang <boyuan.zhang@amd.com> > > Enable system interrupt for jrbc during engine starting time. > > Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > index 4fccb21..22c1588 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > @@ -595,6 +595,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) > struct amdgpu_ring *ring = &adev->vcn.ring_dec; > uint32_t rb_bufsz, tmp; > uint32_t lmi_swap_cntl; > + uint32_t reg_temp; > int i, j, r; > > /* disable byte swapping */ > @@ -700,6 +701,11 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) > (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), > ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); > > + /* enable system interrupt for JRBC*/ > + reg_temp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN)); > + reg_temp |= UVD_SYS_INT_EN__UVD_JRBC_EN_MASK; > + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), reg_temp); Here you could use below instead. WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); Ether way, the whole series are Acked-by: Leo Liu <leo.liu@amd.com> > + > /* clear the bit 4 of VCN_STATUS */ > WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, > ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); > @@ -1754,7 +1760,7 @@ static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { > > static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) > { > - adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 1; > + adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2; > adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs; > } > </div> </div> </body> </html>