<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=us-ascii">
<style type="text/css" style="display:none;"><!-- P {margin-top:0;margin-bottom:0;} --></style>
</head>
<body dir="ltr">
<div id="divtagdefaultwrapper" style="font-size:12pt;color:#000000;font-family:Calibri,Helvetica,sans-serif;" dir="ltr">
<p style="margin-top:0;margin-bottom:0">Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
</p>
</div>
<hr style="display:inline-block;width:98%" tabindex="-1">
<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Evan Quan <evan.quan@amd.com><br>
<b>Sent:</b> Thursday, August 16, 2018 10:36:32 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Deucher, Alexander; Xu, Feifei; Quan, Evan<br>
<b>Subject:</b> [PATCH] drm/amd/powerplay: set correct base for THM/NBIF/MP1 IP</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">Set correct address base for vega20.<br>
<br>
Change-Id: I7435980e2ca156ee2b443a97899d40aaba4876cb<br>
Signed-off-by: Evan Quan <evan.quan@amd.com><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 3 +++<br>
 1 file changed, 3 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c<br>
index 52778de93ab0..2d4473557b0d 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c<br>
@@ -38,6 +38,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev)<br>
                 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));<br>
                 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));<br>
                 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));<br>
+               adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));<br>
                 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));<br>
                 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));<br>
                 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));<br>
@@ -46,6 +47,8 @@ int vega20_reg_base_init(struct amdgpu_device *adev)<br>
                 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));<br>
                 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));<br>
                 adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));<br>
+               adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));<br>
+               adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));<br>
         }<br>
         return 0;<br>
 }<br>
-- <br>
2.18.0<br>
<br>
</div>
</span></font></div>
</body>
</html>