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<p style="margin-top:0;margin-bottom:0"><font size="2"><span style="font-size:11pt;">Acked-by: Alex Deucher <alexander.deucher@amd.com></span></font><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Rex Zhu <Rex.Zhu@amd.com><br>
<b>Sent:</b> Wednesday, August 22, 2018 2:41:19 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org; Francis, David; Wentland, Harry<br>
<b>Cc:</b> Zhu, Rex<br>
<b>Subject:</b> [PATCH v2] drm/amd/display: Fix bug use wrong pp interface</font>
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<div class="PlainText">Used wrong pp interface, the original interface is<br>
exposed by dpm on SI and paritial CI.<br>
<br>
Pointed out by Francis David <david.francis@amd.com><br>
<br>
v2: dal only need to set min_dcefclk and min_fclk to smu.<br>
    so use display_clock_voltage_request interface,<br>
    instand of update all display configuration.<br>
<br>
Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com><br>
---<br>
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 12 ++++++++++--<br>
 1 file changed, 10 insertions(+), 2 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c<br>
index e5c5b0a..7811d60 100644<br>
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c<br>
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c<br>
@@ -480,12 +480,20 @@ void pp_rv_set_display_requirement(struct pp_smu *pp,<br>
 {<br>
         const struct dc_context *ctx = pp->dm;<br>
         struct amdgpu_device *adev = ctx->driver_context;<br>
+       void *pp_handle = adev->powerplay.pp_handle;<br>
         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;<br>
+       struct pp_display_clock_request clock = {0};<br>
 <br>
-       if (!pp_funcs || !pp_funcs->display_configuration_changed)<br>
+       if (!req || !pp_funcs || !pp_funcs->display_clock_voltage_request)<br>
                 return;<br>
 <br>
-       amdgpu_dpm_display_configuration_changed(adev);<br>
+       clock.clock_type = amd_pp_dcf_clock;<br>
+       clock.clock_freq_in_khz = req->hard_min_dcefclk_khz;<br>
+       pp_funcs->display_clock_voltage_request(pp_handle, &clock);<br>
+<br>
+       clock.clock_type = amd_pp_f_clock;<br>
+       clock.clock_freq_in_khz = req->hard_min_fclk_khz;<br>
+       pp_funcs->display_clock_voltage_request(pp_handle, &clock);<br>
 }<br>
 <br>
 void pp_rv_set_wm_ranges(struct pp_smu *pp,<br>
-- <br>
1.9.1<br>
<br>
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